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Rev Age Author Path Log message Diff
1780 6712 d 4 h jermar /kernel/trunk/ Replace old __u?? types with respective C99 variants (e.g. uint32_t, int64_t, uintptr_t etc.).  
1702 6733 d 7 h cejka /kernel/trunk/ Kernel doxygen comments updated.  
1423 6750 d 7 h jermar /kernel/trunk/ Update page fault handlers to distinguish between different access modes that had caused the page fault.  
1380 6757 d 1 h jermar /kernel/trunk/ Turn address space lock, address space area lock and
page_ht_lock into mutexes.
 
1108 6815 d 23 h jermar /kernel/trunk/ Small PTE_* macros and SET_PTL0_ADDRESS macro changes.  
977 6824 d 7 h jermar /kernel/trunk/ Add sys_mremap() syscall.  
902 6837 d 8 h jermar /kernel/trunk/ ia64 work.
More capable TLB miss handlers.
The ia64 kernel now passes mm/mapping1 test.

Fix generic hash table to properly initialize lists.

Change page_ht() to properly initialize inserted PTE's.
Change format of generic page hash table PTE's.
 
793 6860 d 6 h jermar /kernel/trunk/ Use hash_table_get_instance instead of list_get_instance.
Rename page_operations to page_mapping_operations.
Rename page_pt_operations to pt_mapping_operations.
Rename page_ht_operations to ht_mapping_operations.
 
792 6860 d 7 h jermar /kernel/trunk/ Page hash table architectures now use generic hash table to manage
mappings.
 
756 6865 d 21 h jermar /kernel/trunk/ Memory management work.
Remove the last (i.e. 'root') argument from page_mapping_insert() and page_mapping_find().
Page table address is now extracted from the first (i.e. 'as') argument.
Add a lot of infrastructure to make the above possible.
sparc64 is now broken, most likely because of insufficient identity mapping of physical memory.
 
746 6871 d 7 h jermar /kernel/trunk/ Page hash table modifications.  
699 6887 d 8 h jermar /kernel/trunk/ Memory management work.
Proto-interface and dummy implementation of generic page hash table subsytem.
 
684 6889 d 6 h jermar /kernel/trunk/ Memory management work.
Move generic 4-level page table interface to genarch
and enable architectures to use different virtual memory
mechanisms (e.g. page hash tables).
Start page hash table support.
Switch ia64 and sparc64 to page hash tables.
Other architectures keep on using 4-level page table interface.