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1138 6850 d 5 h jermar /kernel/trunk/ CPU stacks must have two frames on ia64.
Make sure both thread stack frames are mapped in before_thread_runs_arch().
Take STACK_FRAMES into account during kernel memory layout initialization in main_bsp().		  
1056 6861 d 3 h jermar /kernel/trunk/arch/ia64/src/ Slightly optimized version of ivt.S.  
1053 6861 d 4 h vana /kernel/trunk/ Itanium FPU Lazy context switching... but not so much tested  
1023 6862 d 3 h vana /kernel/trunk/ Itanium FPU active context switch  
993 6863 d 1 h jermar /kernel/trunk/arch/ia64/ Fix bug in switch to userspace on ia64: ensure start in bank 1.
Fix bug in tlb_invalidate_all() that cause interrupts to be unconditionally enabled.
Optimize context switching by discarding packed attribute of context structures.		  
979 6863 d 7 h vana /kernel/trunk/arch/ia64/ Itanium FPU context save/restore  
962 6864 d 0 h jermar /kernel/trunk/arch/ia64/ ia64 work.
Support for __SYSCALL4.
Fix user stack initial address.		  
921 6868 d 4 h jermar /kernel/trunk/arch/ia64/ ia64 work.
Userspace is now working.
There is an unrelated show stopper, however.		  
919 6868 d 9 h jermar /kernel/trunk/ ia64 work.
Changes to make userspace work (kernel part).
Use ski.conf from contrib directory to run Ski.

There is actually no appropriate syscall handler yet.		  
916 6870 d 10 h jermar /kernel/trunk/arch/ia64/src/ ia64 work.
Support switch from userspace register stack in heavyweight handler.		  
915 6870 d 11 h jermar /kernel/trunk/arch/ia64/ ia64 work.
- Another item had to be allocated on stack to remember new value written to ar.bspstore.
Fix heavyweight interruption handler to calculate RSC.loadrs from the new value of ar.bspstore
instead from the old one.
Uncomment instructions switching ar.bspstore.
- Configure kernel with 512M of memory.		  
912 6872 d 1 h jermar /kernel/trunk/ ia64 work.

ivt.S:
Detect userspace stack in heavyweight handler and switch to kernel stack.
Remember the old stack pointer.
As for register stack, kernel stack is assumed still.
Fix alignment issues that showed when STACK_ITEMS was odd.
Fix ld8 instruction that did subtraction of 8 instead of addition of 8.

scheduler.c:
Change before_thread_runs_arch() to calculate address of top of the stack
for the interrupt handler.		  
911 6872 d 5 h jermar /kernel/trunk/arch/ia64/ ia64 work.

Change heavyweight interrupt handler to use bank 0 registers instead of AR.KR0 and AR.KR1.
This prevents userspace from the possibility to see what addresses are being used by kernel.

Store kernel stack address in bank 0 r23 instead of AR.KR7. Again, userspace will not be
able to read the address of its kernel stack.

Increase FRAME_SIZE to 64K as this is the first supported page size in which will fit
thread's combined register and memory stack. (RSE can write out as many as 16K.)		  
899 6877 d 4 h jermar /kernel/trunk/arch/ ia64 work.
Add dummy TLB fault handlers.
Improve code reuse in arch/mm/tlb.c.		  
534 6963 d 2 h jermar / Rename HelenOS/SPARTAN to HelenOS/kernel again.  
532 6963 d 2 h jermar / Revert renaming of HelenOS/SPARTAN to HelenOS/kernel because of important pending patch.  
501 6975 d 6 h jermar / Rename HelenOS/SPARTAN to HelenOS/kernel.  
478 6986 d 4 h jermar /SPARTAN/trunk/ Re-aply mistakenly reverted changes.  
477 6986 d 7 h vana /SPARTAN/trunk/ Atomic inc & dec functions synchronized on all ia32,ia64 and mips platforms. Now there are 3 versions which returns no value, new value and old value och changed variable.  
473 6987 d 23 h jermar /SPARTAN/trunk/arch/ia64/src/ ia64 work.
Comment some offending steps of heavyweight interrupt handler regarding RSE switching.
With this change, ia64 will do well on tests rwlock #4 and thread #1.
Cleanup.		  

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