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Rev Age Author Path Log message Diff
1780 6710 d 5 h jermar /kernel/trunk/ Replace old __u?? types with respective C99 variants (e.g. uint32_t, int64_t, uintptr_t etc.).  
1702 6731 d 8 h cejka /kernel/trunk/ Kernel doxygen comments updated.  
1675 6735 d 9 h jermar /kernel/trunk/arch/ia64/ On ia64, purge DTR entry before overwriting it with new contents.  
1511 6742 d 8 h palkovsky /kernel/trunk/arch/ Remove __address from include file included by uspace  
1290 6770 d 8 h vana /kernel/trunk/arch/ VESA detection failure fix.

(Some headers)		  
1210 6784 d 9 h vana /kernel/trunk/ Incomplete VHPT walker support for Itanium  
1138 6809 d 5 h jermar /kernel/trunk/ CPU stacks must have two frames on ia64.
Make sure both thread stack frames are mapped in before_thread_runs_arch().
Take STACK_FRAMES into account during kernel memory layout initialization in main_bsp().		  
1108 6814 d 0 h jermar /kernel/trunk/ Small PTE_* macros and SET_PTL0_ADDRESS macro changes.  
1070 6819 d 12 h jermar /kernel/trunk/ More checks for address space area conflicts.  
967 6822 d 12 h palkovsky /kernel/trunk/ Allowed userspace to include page.h.  
958 6823 d 2 h jermar /kernel/trunk/ Nicer ia32 interrupt handlers and structures holding interrupted context data.
Unify the name holding interrupted context data on all architectures to be istate.		  
945 6824 d 1 h vana /kernel/trunk/arch/ia64/  
944 6824 d 2 h vana /kernel/trunk/ Itanium tlb_invalidate_pages  
940 6824 d 3 h jermar /kernel/trunk/ Get rid of unneeded macros.
Their functionality has been replaced by the ELF loader.		  
935 6824 d 5 h vana /kernel/trunk/ Two frame stack (standard stack + RSE) on Itanium  
919 6827 d 10 h jermar /kernel/trunk/ ia64 work.
Changes to make userspace work (kernel part).
Use ski.conf from contrib directory to run Ski.

There is actually no appropriate syscall handler yet.		  
915 6829 d 12 h jermar /kernel/trunk/arch/ia64/ ia64 work.
- Another item had to be allocated on stack to remember new value written to ar.bspstore.
Fix heavyweight interruption handler to calculate RSC.loadrs from the new value of ar.bspstore
instead from the old one.
Uncomment instructions switching ar.bspstore.
- Configure kernel with 512M of memory.		  
911 6831 d 6 h jermar /kernel/trunk/arch/ia64/ ia64 work.

Change heavyweight interrupt handler to use bank 0 registers instead of AR.KR0 and AR.KR1.
This prevents userspace from the possibility to see what addresses are being used by kernel.

Store kernel stack address in bank 0 r23 instead of AR.KR7. Again, userspace will not be
able to read the address of its kernel stack.

Increase FRAME_SIZE to 64K as this is the first supported page size in which will fit
thread's combined register and memory stack. (RSE can write out as many as 16K.)		  
903 6834 d 4 h jermar /kernel/trunk/arch/ia64/ ia64 work.
Add code needed for running multiple address spaces and location of kernel stack
after switch from userspace.		  
902 6835 d 9 h jermar /kernel/trunk/ ia64 work.
More capable TLB miss handlers.
The ia64 kernel now passes mm/mapping1 test.

Fix generic hash table to properly initialize lists.

Change page_ht() to properly initialize inserted PTE's.
Change format of generic page hash table PTE's.		  

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