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Rev Age Author Path Log message Diff
1036 6816 d 2 h decky /kernel/trunk/arch/mips32/ grow init size  
1034 6816 d 2 h decky /kernel/trunk/contrib/conf/ more realistic simulated CPU frequency  
1032 6816 d 13 h jermar /kernel/trunk/generic/ mmap() syscall.  
1029 6816 d 13 h palkovsky /kernel/trunk/generic/src/ipc/ Fixed bad locking.  
1027 6816 d 13 h palkovsky /kernel/trunk/ Implemented callback IPC call (connect_to_me).  
1026 6816 d 13 h jermar /kernel/trunk/generic/ Support only anonymous address space areas.  
1025 6816 d 14 h palkovsky /kernel/trunk/generic/src/proc/ Fix bug that made task_run_program to always run init.  
1024 6816 d 18 h jermar /kernel/trunk/ Redefine semantics of unary atomic operations.
Add test to verify that an architecture understands the semantics correctly.		  
1023 6816 d 19 h vana /kernel/trunk/ Itanium FPU active context switch  
1021 6816 d 19 h jermar /kernel/trunk/ Hopefully final version of interrupt handlers for amd64 and ia32.
amd64 has been especially tricky to debug.
Error code detection is now done in compile time.		  
1020 6816 d 20 h vana /kernel/trunk/test/fpu/fpu1/ () patch for FPU 1 test  
1019 6816 d 21 h vana /kernel/trunk/arch/ia32/ ia32 MMX and SSEx support  
1017 6816 d 22 h decky /kernel/trunk/ mips: remove load.bin
remove arch/boot infrastructure		  
1016 6816 d 22 h jermar /kernel/trunk/arch/ia32/src/ Improved ia32 interrupt handlers.  
1012 6817 d 0 h palkovsky /kernel/trunk/ Allow correct rebuilding based on boot architecture.  
1008 6817 d 1 h jermar /kernel/trunk/ Fix bug in ia32 interrupt handlers.
Handlers for interrupts greater than 31 wrapped the shift around and thus failed to correctly identify
the need to emulate error word.		  
1007 6817 d 1 h decky /kernel/trunk/ ppc32: preemptive scheduling works now
FPU context saving disabled for now		  
1005 6817 d 1 h palkovsky /kernel/trunk/generic/ Added support for taskid.  
1004 6817 d 12 h decky /kernel/trunk/ ppc32: basic exception and interrupt handling  
1002 6817 d 12 h jermar /kernel/trunk/generic/ More lightweighed TLB shootdown implementation.  

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