| Rev |
Age |
Author |
Path |
Log message |
Diff |
| 4605 |
5604 d 3 h |
decky |
/branches/snapshot/ |
add task snapshoting branch |
|
| 4315 |
5675 d 20 h |
jermar |
/trunk/ |
Replace non-canonical B instructions with BA %xcc.
Fix one occurrence of deprecated Bicc instruction. |
|
| 4282 |
5682 d 6 h |
decky |
/trunk/kernel/arch/sparc64/ |
repair two glitches in memory management
(no beer today :)) |
|
| 4277 |
5683 d 1 h |
jermar |
/trunk/kernel/arch/sparc64/ |
On sparc64, do fast indentity mapping only for physical memory.
For addresses above physical memory, such as I/O devices,
fall through to the C miss handler and map the memory noncacheably.
Replace deprecated Bicc instructions with proper Bcc instructions. |
|
| 3672 |
5812 d 21 h |
jermar |
/trunk/ |
Merge sparc branch to trunk. |
|
| 3482 |
5876 d 20 h |
jermar |
/trunk/kernel/arch/sparc64/ |
Do not allocate full page for the uspace window buffer.
Instead, allocate only the bare minimum to fit NWINDOWS - 1
uspace windows and to satisfy alignment requirements. |
|
| 3463 |
5889 d 1 h |
jermar |
/trunk/kernel/arch/sparc64/ |
Populate all sparc64 trap table slots belonging to trap_instruction_n. |
|
| 2610 |
6198 d 0 h |
jermar |
/trunk/ |
Support for six syscall arguments for sparc64.
There is a minor stability issue which needs to be fixed (kernel panics upon entering kconsole from the
console task). |
|
| 2231 |
6419 d 0 h |
jermar |
/trunk/kernel/arch/sparc64/ |
Fix a nasty bug in the TLB miss handlers on sparc64.
After we no longer lock the kernel stack in the DTLB,
there is a real danger of nested DTLB misses. The nested
miss can very easily clobber the DTLB Tag Access register.
Therefore, the original miss may not read this register, but
it has to receive its value as an argument. The argument
value is saved in the trap table when it is guaranteed that
the nested TLB miss will not occur. |
|
| 2089 |
6490 d 3 h |
decky |
/trunk/ |
huge type system cleanup
remove cyclical type dependencies across multiple header files
many minor coding style fixes |
|
| 2071 |
6500 d 20 h |
jermar |
/trunk/ |
(c) versus (C) |
|
| 2068 |
6508 d 3 h |
jermar |
/trunk/kernel/ |
Formatting and indentation fixes. |
|
| 1978 |
6561 d 20 h |
jermar |
/trunk/ |
sparc64 code to support physical memory that starts on non-zero addresses.
Still needs to be tested on systems with such setup. |
|
| 1954 |
6583 d 19 h |
jermar |
/trunk/ |
Minor changes. Some coding style fixes and also a type (tee vs. tree).
One AS -> as change. |
|
| 1915 |
6601 d 20 h |
jermar |
/trunk/kernel/ |
A quote from from SPARC V9 specification:
The Y register is deprecated; it is provided only for compatibility with previous versions
of the architecture. It should not be used in new SPARC-V9 software. It is
recommended that all instructions that reference the Y register (i.e., SMUL,
SMULcc, UMUL, UMULcc, MULScc, SDIV, SDIVcc, UDIV, UDIVcc, RDY, and
WRY) be avoided. See the appropriate pages in Appendix A, “Instruction Definitions,”
for suitable substitute instructions.
Still gcc is generating code which uses Y and some of the instructions above.
This change modifies the preemptible_handler() to preserve the Y register
across preemption. |
|
| 1911 |
6603 d 18 h |
jermar |
/trunk/kernel/ |
Add support for interrupt mapping in the Sabre PCI controller.
Add support for PCI and EBUS interrupt mapping via the OpenFirmware device tree.
Unfortunatelly, the code is not capable enough to earn single ns16550 interrupt.
I suspect something needs to be enabled in the EBUS registers. |
|
| 1904 |
6612 d 1 h |
jermar |
/trunk/kernel/ |
IPI/cross-call support for sparc64.
SMP on sparc64 is now fully supported. |
|
| 1891 |
6621 d 18 h |
jermar |
/trunk/kernel/ |
sparc64 work:
- Experimental support for TSB (Translation Storage Buffer). |
|
| 1888 |
6625 d 23 h |
jermar |
/trunk/ |
C99 compliant header guards (hopefully) everywhere in the kernel.
Formatting and indentation changes.
Small improvements in sparc64. |
|
| 1887 |
6626 d 3 h |
jermar |
/trunk/kernel/arch/sparc64/ |
When creating TLB mapping for the sparc64 kernel, enable CV (cacheable virtually) bit.
Also install locked mappings only in context 0. |
|