| Rev |
Age |
Author |
Path |
Log message |
Diff |
| 4581 |
5607 d 12 h |
mejdrech |
/branches/network/ |
Net: synchronized with trunk rev.4580 |
|
| 4327 |
5670 d 22 h |
mejdrech |
/branches/network/ |
Net: *merged with trunk 4326, +ne2k irq debug |
|
| 4263 |
5686 d 11 h |
mejdrech |
/branches/network/ |
Net: merged with trunk:4261 |
|
| 4153 |
5708 d 11 h |
mejdrech |
/branches/network/ |
Networking: merged with trunk changes |
|
| 3386 |
5904 d 14 h |
decky |
/branches/network/ |
add new network branch (copy of current trunk) |
|
| 3133 |
5986 d 10 h |
jermar |
/trunk/kernel/arch/ |
Add smc_coherence() macro to all architectures.
So far, only amd64, ia32, ia64 and sparc64 are implemented. |
|
| 3104 |
5993 d 23 h |
svoboda |
/trunk/kernel/ |
Declare arguments for memstr.h operations as pointers instead of uintptr_t. |
|
| 2745 |
6093 d 19 h |
decky |
/trunk/ |
code cleanup (mostly signed/unsigned)
allow extra compiler warnings |
|
| 2725 |
6114 d 16 h |
decky |
/trunk/kernel/ |
remove config.memory_size, get_memory_size() and memory_init.{c|d}
the amount of available memory can be calculated from the sizes of the zones
add FRAMES2SIZE, SIZE2KB and SIZE2MB functions/macros (code readability) |
|
| 2462 |
6359 d 10 h |
jermar |
/trunk/kernel/ |
Replace gcc-specific __FUNCTION__ with C99 __func__.
suncc's xregs=no%float can be used only on sparc64. |
|
| 2272 |
6407 d 12 h |
jermar |
/trunk/kernel/ |
Indentation and formatting fixes. |
|
| 2267 |
6409 d 11 h |
jermar |
/trunk/kernel/arch/sparc64/src/mm/ |
Fix indentation. |
|
| 2266 |
6409 d 12 h |
jermar |
/trunk/kernel/arch/sparc64/src/mm/ |
Add few assertions to tsb.c and clean it up a little bit. |
|
| 2252 |
6411 d 10 h |
jermar |
/trunk/kernel/arch/sparc64/src/mm/ |
Move one MEMBAR instruction from a delay slot,
which is, due to SF Erratum #51, a potentionally
dangerous place for a MEMBAR to be. |
|
| 2231 |
6417 d 14 h |
jermar |
/trunk/kernel/arch/sparc64/ |
Fix a nasty bug in the TLB miss handlers on sparc64.
After we no longer lock the kernel stack in the DTLB,
there is a real danger of nested DTLB misses. The nested
miss can very easily clobber the DTLB Tag Access register.
Therefore, the original miss may not read this register, but
it has to receive its value as an argument. The argument
value is saved in the trap table when it is guaranteed that
the nested TLB miss will not occur. |
|
| 2170 |
6426 d 8 h |
jermar |
/trunk/kernel/ |
Simplify synchronization in as_switch().
The function was oversynchronized, which
was causing deadlocks on the address
space mutex.
Now, address spaces can only be switched
when the asidlock is held. This also protects
stealing of ASIDs. No other synchronization
is necessary. |
|
| 2161 |
6428 d 11 h |
jermar |
/trunk/kernel/arch/sparc64/src/mm/ |
Fix TSB bug during TSB refill.
When one wants to enable a TSB entry, he or she should set the
entry invalid bit to false, as opposed to setting it to true. |
|
| 2144 |
6429 d 9 h |
jermar |
/trunk/kernel/arch/sparc64/src/mm/ |
Fix TSB size. |
|
| 2141 |
6430 d 7 h |
jermar |
/trunk/ |
The Ultimate Solution To Illegal Virtual Aliases.
It is better to avoid them completely than to fight them.
Switch the sparc64 port to 16K pages. The TLBs and TSBs
continue to operate with 8K pages only. Page tables and
other generic parts operate with 16K pages.
Because the MMU doesn't support 16K directly, each 16K
page is emulated by a pair of 8K pages. With 16K pages,
illegal aliases cannot be created in 16K D-cache. |
|
| 2134 |
6431 d 11 h |
jermar |
/trunk/kernel/ |
Reworked handling of illegal virtual aliases caused by frame reuse.
We moved the incomplete handling from backend's frame method to
backend's page_fault method. The page_fault method is the one that
can create an illegal alias if it writes the userspace frame using
kernel address with a different page color than the page to which is
this frame mapped in userspace. When we detect this, we do D-cache
shootdown on all processors (!!!).
If we add code that accesses userspace memory from kernel address
space, we will have to check for illegal virtual aliases at all such
places.
I tested this on a 4-way simulated E6500 and a real-world Ultra 5,
which has unfortunatelly only one processor.
This solves ticket #26. |
|