| Rev |
Age |
Author |
Path |
Log message |
Diff |
| 4130 |
5712 d 18 h |
rimsky |
/branches/sparc/ |
Cleanup of the Niagara port. The main purpose of these changes is to make it easy to find out which code is generic, which is sun4u-specific and which is sun4v-specific. |
|
| 4129 |
5713 d 14 h |
rimsky |
/branches/sparc/kernel/arch/sparc64/ |
Implemented missing features in Niagara memory management, minor cleanup. |
|
| 3993 |
5725 d 15 h |
rimsky |
/branches/sparc/kernel/ |
Implemented preemptible trap handler for userspace (including syscalls - did not forget enabling interrupts for them) and the ralated stuff. Implemented handlers of instruction/data MMU miss/protection. Now some userspace tasks are run; there are, however, still some bugs causing unexpected data MMU misses. |
|
| 3862 |
5750 d 16 h |
rimsky |
/branches/sparc/kernel/ |
Changed the structure of header files, which have sun4u and sun4v versions. Implemented some sun4v TSB functions. |
|
| 3835 |
5755 d 16 h |
rimsky |
/branches/sparc/kernel/arch/sparc64/ |
Niagara: Implemented (and debugged) installing identity mapping for kernel. Now all the kernel tests pass on Simics. |
|
| 3771 |
5783 d 17 h |
rimsky |
/branches/sparc/kernel/arch/sparc64/ |
Forgotten files comitted to repository. |
|
| 3770 |
5783 d 17 h |
rimsky |
/branches/sparc/ |
Working on Niagara port - TLB initialization, MMU fault status area initialization, hypercall enhancement, modified tick.c so that the (hyperprivileged) TICK register does not have to be accessed. Now the initialization phase proceeds, but some parts of it are omitted for now (e.g. CPU initialization). |
|
| 3743 |
5791 d 1 h |
rimsky |
/branches/sparc/ |
Started to implement support for sun4v. Bootloader adapted to autodetect the architecture (sun4u, sun4v). Some generic sparc64 kernel files split into sun4u and sun4v versions (but the sun4u is still the default in many cases - in order to keep the code compilable). Implemented taking over the MMU. Implemented routines for performing the hypervisor API calls. Implemented a trivial standard output driver. HelenOS banner can now be printed from the kernel on Niagara. |
|
| 3742 |
5791 d 2 h |
rimsky |
/branches/sparc/ |
The sparc branch synchronized with trunk at revision 3722 (trunk@3722). |
|
| 3618 |
5824 d 16 h |
rimsky |
/branches/sparc/ |
Support for framebuffers, where the first pixel is mapped to a different address than the OBP 'reg' property claims. Cleanup, comments, C-style. |
|
| 3607 |
5825 d 14 h |
rimsky |
/branches/sparc/ |
Cleanup and minor fixes. |
|
| 3591 |
5830 d 0 h |
rimsky |
/branches/sparc/ |
Making the code compatible also with US-IV (US-IV+) - TLB size based on CPU autodetection, cleanup of code waking up APs. General cleanup. |
|
| 3493 |
5860 d 17 h |
rimsky |
/branches/sparc/ |
More changes making the code US-III-conformant (mainly in mm). |
|
| 3489 |
5867 d 19 h |
rimsky |
/branches/sparc/ |
More files made conform the US-III specification. (Changes concern mainly TSB.) |
|
| 3467 |
5885 d 17 h |
rimsky |
/branches/sparc/ |
SMP and CPU initialiation modified to work even with Serengeti OFW tree layout; support for output to the Simics CLI console added (see my blog); some header files modified to conform US-III definition. Now HelenOS (on the sample configuration - usiii.simics) is able to run some userspace tasks. |
|
| 3450 |
5889 d 17 h |
rimsky |
/branches/sparc/kernel/arch/sparc64/ |
Made tlb.h conform US-III specification. |
|
| 3440 |
5891 d 2 h |
rimsky |
/branches/sparc/kernel/arch/sparc64/ |
TLB modifications in order to make functions tlb_print and tlb_invalidate_all work correctly in US-III. |
|
| 3343 |
5919 d 21 h |
decky |
/branches/sparc/ |
add sparc branch |
|
| 3233 |
5942 d 23 h |
decky |
/trunk/ |
remove dummy page coloring facility, which is currenty not used |
|
| 3145 |
5985 d 6 h |
jermar |
/trunk/kernel/arch/sparc64/include/ |
On sparc64, when the operand to the FLUSH instruction doesn't matter, the
instruction's semantics is to flush the pipeline. |
|
| 3133 |
5986 d 18 h |
jermar |
/trunk/kernel/arch/ |
Add smc_coherence() macro to all architectures.
So far, only amd64, ia32, ia64 and sparc64 are implemented. |
|
| 2725 |
6115 d 0 h |
decky |
/trunk/kernel/ |
remove config.memory_size, get_memory_size() and memory_init.{c|d}
the amount of available memory can be calculated from the sizes of the zones
add FRAMES2SIZE, SIZE2KB and SIZE2MB functions/macros (code readability) |
|
| 2721 |
6116 d 0 h |
decky |
/trunk/kernel/ |
convert e820list to a generic physmem command |
|
| 2231 |
6417 d 22 h |
jermar |
/trunk/kernel/arch/sparc64/ |
Fix a nasty bug in the TLB miss handlers on sparc64.
After we no longer lock the kernel stack in the DTLB,
there is a real danger of nested DTLB misses. The nested
miss can very easily clobber the DTLB Tag Access register.
Therefore, the original miss may not read this register, but
it has to receive its value as an argument. The argument
value is saved in the trap table when it is guaranteed that
the nested TLB miss will not occur. |
|
| 2141 |
6430 d 15 h |
jermar |
/trunk/ |
The Ultimate Solution To Illegal Virtual Aliases.
It is better to avoid them completely than to fight them.
Switch the sparc64 port to 16K pages. The TLBs and TSBs
continue to operate with 8K pages only. Page tables and
other generic parts operate with 16K pages.
Because the MMU doesn't support 16K directly, each 16K
page is emulated by a pair of 8K pages. With 16K pages,
illegal aliases cannot be created in 16K D-cache. |
|
| 2134 |
6431 d 19 h |
jermar |
/trunk/kernel/ |
Reworked handling of illegal virtual aliases caused by frame reuse.
We moved the incomplete handling from backend's frame method to
backend's page_fault method. The page_fault method is the one that
can create an illegal alias if it writes the userspace frame using
kernel address with a different page color than the page to which is
this frame mapped in userspace. When we detect this, we do D-cache
shootdown on all processors (!!!).
If we add code that accesses userspace memory from kernel address
space, we will have to check for illegal virtual aliases at all such
places.
I tested this on a 4-way simulated E6500 and a real-world Ultra 5,
which has unfortunatelly only one processor.
This solves ticket #26. |
|
| 2106 |
6483 d 1 h |
jermar |
/trunk/kernel/ |
Merge as_t structure into one and leave the differring parts in as_genarch_t.
Indentation and formatting changes in header files. |
|
| 2105 |
6487 d 1 h |
decky |
/trunk/kernel/ |
move ipc structures to ipc.h |
|
| 2089 |
6489 d 1 h |
decky |
/trunk/ |
huge type system cleanup
remove cyclical type dependencies across multiple header files
many minor coding style fixes |
|
| 2076 |
6498 d 2 h |
jermar |
/trunk/kernel/ |
Beat the implicit illegal virtual alias created by reusing userspace frames.
In the anonymous and ELF backends, if the architecture has virtually indexed D-cache,
selectively flush cachelines belonging to the frame being freed.
This fixes Ticket #20. |
|
| 2071 |
6499 d 18 h |
jermar |
/trunk/ |
(c) versus (C) |
|
| 2068 |
6507 d 1 h |
jermar |
/trunk/kernel/ |
Formatting and indentation fixes. |
|
| 2065 |
6513 d 16 h |
jermar |
/trunk/kernel/ |
Coding style fixes and formatting improvements. |
|
| 2054 |
6527 d 16 h |
jermar |
/trunk/kernel/ |
Fix important comment in kernel/arch/sparc64/src/proc/scheduler.c.
Improve framebuffer code.
Formatting and indentation fixes. |
|
| 2048 |
6531 d 19 h |
jermar |
/trunk/ |
Formatting and indentation changes. |
|
| 2015 |
6538 d 18 h |
jermar |
/trunk/ |
Rework support for virtually indexed cache.
Instead of repeatedly flushing the data cache, which was a huge overkill, refuse to create an illegal address alias
in the kernel (again) and allocate appropriate page color in userspace instead. Extend the detection also to
SYS_PHYSMEM_MAP syscall.
Add support for tracking physical memory areas mappable by SYS_PHYSMEM_MAP.
Lots of coding style changes. |
|
| 2009 |
6543 d 17 h |
jermar |
/trunk/kernel/ |
Initial support for handling illegal virtual aliases on sparc64. |
|
| 2008 |
6545 d 18 h |
jermar |
/trunk/kernel/arch/sparc64/ |
Add dcache_flush() function that flushes D-Cache on sparc64. |
|
| 2007 |
6546 d 16 h |
jermar |
/trunk/kernel/ |
Introduce page colors. So far, only sparc64 uses correct page color bits. Other architectures have a dummy define
specifying zero bits for a page color.
There is a new check of page color in as_area_share(). Because of lack of support for this in the userspace, the
check has been #ifef'ed out. |
|
| 1978 |
6560 d 18 h |
jermar |
/trunk/ |
sparc64 code to support physical memory that starts on non-zero addresses.
Still needs to be tested on systems with such setup. |
|