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  1. /*
  2.  * Copyright (c) 2006 Martin Decky
  3.  * Copyright (c) 2009 Jiri Svoboda
  4.  * All rights reserved.
  5.  *
  6.  * Redistribution and use in source and binary forms, with or without
  7.  * modification, are permitted provided that the following conditions
  8.  * are met:
  9.  *
  10.  * - Redistributions of source code must retain the above copyright
  11.  *   notice, this list of conditions and the following disclaimer.
  12.  * - Redistributions in binary form must reproduce the above copyright
  13.  *   notice, this list of conditions and the following disclaimer in the
  14.  *   documentation and/or other materials provided with the distribution.
  15.  * - The name of the author may not be used to endorse or promote products
  16.  *   derived from this software without specific prior written permission.
  17.  *
  18.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28.  */
  29.  
  30. /** @addtogroup genarch
  31.  * @{
  32.  */
  33. /** @file
  34.  */
  35.  
  36. #include <genarch/drivers/via-cuda/cuda.h>
  37. #include <console/chardev.h>
  38. #include <ddi/irq.h>
  39. #include <arch/asm.h>
  40. #include <mm/slab.h>
  41. #include <ddi/device.h>
  42. #include <synch/spinlock.h>
  43.  
  44. static void cuda_packet_handle(cuda_instance_t *instance, size_t len);
  45.  
  46. /** B register fields */
  47. enum {
  48.     TREQ    = 0x08,
  49.     TACK    = 0x10,
  50.     TIP = 0x20
  51. };
  52.  
  53. /** IER register fields */
  54. enum {
  55.     IER_SET = 0x80,
  56.     SR_INT  = 0x04
  57. };
  58.  
  59. static irq_ownership_t cuda_claim(irq_t *irq)
  60. {
  61.     cuda_instance_t *instance = irq->instance;
  62.     cuda_t *dev = instance->cuda;
  63.     uint8_t ifr;
  64.  
  65.     ifr = pio_read_8(&dev->ifr);
  66.  
  67.     if ((ifr & SR_INT) != 0)
  68.         return IRQ_ACCEPT;
  69.     else
  70.         return IRQ_DECLINE;
  71. }
  72.  
  73. static void cuda_irq_handler(irq_t *irq)
  74. {
  75.     cuda_instance_t *instance = irq->instance;
  76.     cuda_t *dev = instance->cuda;
  77.     uint8_t b, data;
  78.     size_t pos;
  79.  
  80.     spinlock_lock(&instance->dev_lock);
  81.  
  82.     /* We have received one or more CUDA packets. Process them all. */
  83.     while (true) {
  84.         b = pio_read_8(&dev->b);
  85.  
  86.         if ((b & TREQ) != 0)
  87.             break;  /* No data */
  88.  
  89.         pio_write_8(&dev->b, b & ~TIP);
  90.  
  91.         /* Read one packet. */
  92.  
  93.         pos = 0;
  94.         do {
  95.             data = pio_read_8(&dev->sr);
  96.             b = pio_read_8(&dev->b);
  97.             pio_write_8(&dev->b, b ^ TACK);
  98.  
  99.             if (pos < CUDA_RCV_BUF_SIZE)
  100.                 instance->rcv_buf[pos++] = data;
  101.         } while ((b & TREQ) == 0);
  102.  
  103.         pio_write_8(&dev->b, b | TACK | TIP);
  104.  
  105.         cuda_packet_handle(instance, pos);
  106.     }
  107.  
  108.     spinlock_unlock(&instance->dev_lock);
  109. }
  110.  
  111. static void cuda_packet_handle(cuda_instance_t *instance, size_t len)
  112. {
  113.     uint8_t *data = instance->rcv_buf;
  114.  
  115.     if (data[0] != 0x00 || data[1] != 0x40 || data[2] != 0x2c)
  116.         return;
  117.  
  118.     /* The packet contains one or two scancodes. */
  119.     if (data[3] != 0xff)
  120.         indev_push_character(instance->kbrdin, data[3]);       
  121.     if (data[4] != 0xff)
  122.         indev_push_character(instance->kbrdin, data[4]);
  123. }
  124.  
  125. cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg)
  126. {
  127.     cuda_instance_t *instance
  128.         = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC);
  129.     if (instance) {
  130.         instance->cuda = dev;
  131.         instance->kbrdin = NULL;
  132.  
  133.         spinlock_initialize(&instance->dev_lock, "cuda_dev");
  134.  
  135.         irq_initialize(&instance->irq);
  136.         instance->irq.devno = device_assign_devno();
  137.         instance->irq.inr = inr;
  138.         instance->irq.claim = cuda_claim;
  139.         instance->irq.handler = cuda_irq_handler;
  140.         instance->irq.instance = instance;
  141.         instance->irq.cir = cir;
  142.         instance->irq.cir_arg = cir_arg;
  143.     }
  144.    
  145.     return instance;
  146. }
  147.  
  148. void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
  149. {
  150.     ASSERT(instance);
  151.     ASSERT(kbrdin);
  152.  
  153.     instance->kbrdin = kbrdin;
  154.     irq_register(&instance->irq);
  155.  
  156.     /* Enable SR interrupt. */
  157.     pio_write_8(&instance->cuda->ier, IER_SET | SR_INT);
  158. }
  159.  
  160. /** @}
  161.  */
  162.