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  1. /*
  2.  * Copyright (c) 2006 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <smp/ipi.h>
  36. #include <cpu.h>
  37. #include <arch.h>
  38. #include <arch/cpu.h>
  39. #include <arch/asm.h>
  40. #include <config.h>
  41. #include <mm/tlb.h>
  42. #include <arch/mm/cache.h>
  43. #include <arch/interrupt.h>
  44. #include <arch/trap/interrupt.h>
  45. #include <arch/barrier.h>
  46. #include <preemption.h>
  47. #include <time/delay.h>
  48. #include <panic.h>
  49.  
  50. /** Invoke function on another processor.
  51.  *
  52.  * Currently, only functions without arguments are supported.
  53.  * Supporting more arguments in the future should be no big deal.
  54.  *
  55.  * Interrupts must be disabled prior to this call.
  56.  *
  57.  * @param mid MID of the target processor.
  58.  * @param func Function to be invoked.
  59.  */
  60. static void cross_call(int mid, void (* func)(void))
  61. {
  62.     uint64_t status;
  63.     bool done;
  64.  
  65.     /*
  66.      * This function might enable interrupts for a while.
  67.      * In order to prevent migration to another processor,
  68.      * we explicitly disable preemption.
  69.      */
  70.    
  71.     preemption_disable();
  72.    
  73.     status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
  74.     if (status & INTR_DISPATCH_STATUS_BUSY)
  75.         panic("Interrupt Dispatch Status busy bit set\n");
  76.    
  77.     do {
  78.         asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t)
  79.             func);
  80.         asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
  81.         asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
  82.         asi_u64_write(ASI_UDB_INTR_W,
  83.             (mid << INTR_VEC_DISPATCH_MID_SHIFT) |
  84.             ASI_UDB_INTR_W_DISPATCH, 0);
  85.    
  86.         membar();
  87.        
  88.         do {
  89.             status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
  90.         } while (status & INTR_DISPATCH_STATUS_BUSY);
  91.        
  92.         done = !(status & INTR_DISPATCH_STATUS_NACK);
  93.         if (!done) {
  94.             /*
  95.              * Prevent deadlock.
  96.              */        
  97.             (void) interrupts_enable();
  98.             delay(20 + (tick_read() & 0xff));
  99.             (void) interrupts_disable();
  100.         }
  101.     } while (done);
  102.    
  103.     preemption_enable();
  104. }
  105.  
  106. /*
  107.  * Deliver IPI to all processors except the current one.
  108.  *
  109.  * The sparc64 architecture does not support any group addressing
  110.  * which is found, for instance, on ia32 and amd64. Therefore we
  111.  * need to simulate the broadcast by sending the message to
  112.  * all target processors step by step.
  113.  *
  114.  * We assume that interrupts are disabled.
  115.  *
  116.  * @param ipi IPI number.
  117.  */
  118. void ipi_broadcast_arch(int ipi)
  119. {
  120.     int i;
  121.    
  122.     void (* func)(void);
  123.    
  124.     switch (ipi) {
  125.     case IPI_TLB_SHOOTDOWN:
  126.         func = tlb_shootdown_ipi_recv;
  127.         break;
  128. #if (defined(CONFIG_SMP) && (defined(CONFIG_VIRT_IDX_DCACHE)))
  129.     case IPI_DCACHE_SHOOTDOWN:
  130.         func = dcache_shootdown_ipi_recv;
  131.         break;
  132. #endif
  133.     default:
  134.         panic("Unknown IPI (%d).\n", ipi);
  135.         break;
  136.     }
  137.    
  138.     /*
  139.      * As long as we don't support hot-plugging
  140.      * or hot-unplugging of CPUs, we can walk
  141.      * the cpus array and read processor's MID
  142.      * without locking.
  143.      */
  144.    
  145.     for (i = 0; i < config.cpu_active; i++) {
  146.         if (&cpus[i] == CPU)
  147.             continue;       /* skip the current CPU */
  148.  
  149.         cross_call(cpus[i].arch.mid, func);
  150.     }
  151. }
  152.  
  153. /** @}
  154.  */
  155.