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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __sparc64_TLB_H__
  30. #define __sparc64_TLB_H__
  31.  
  32. #include <arch/mm/tte.h>
  33.  
  34. /** I-MMU ASIs. */
  35. #define ASI_IMMU            0x50
  36. #define ASI_IMMU_TSB_8KB_PTR_REG    0x51   
  37. #define ASI_IMMU_TSB_64KB_PTR_REG   0x52
  38. #define ASI_ITLB_DATA_IN_REG        0x54
  39. #define ASI_ITLB_DATA_ACCESS_REG    0x55
  40. #define ASI_ITLB_TAG_READ_REG       0x56
  41. #define ASI_IMMU_DEMAP          0x57
  42.  
  43. /** Virtual Addresses within ASI_IMMU. */
  44. #define VA_IMMU_TAG_TARGET      0x0 /**< IMMU tag target register. */
  45. #define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
  46. #define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
  47. #define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
  48.  
  49. /** D-MMU ASIs. */
  50. #define ASI_DMMU            0x58
  51. #define ASI_DMMU_TSB_8KB_PTR_REG    0x59   
  52. #define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
  53. #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
  54. #define ASI_DTLB_DATA_IN_REG        0x5c
  55. #define ASI_DTLB_DATA_ACCESS_REG    0x5d
  56. #define ASI_DTLB_TAG_READ_REG       0x5e
  57. #define ASI_DMMU_DEMAP          0x5f
  58.  
  59. /** Virtual Addresses within ASI_DMMU. */
  60. #define VA_DMMU_TAG_TARGET      0x0 /**< DMMU tag target register. */
  61. #define VA_PRIMARY_CONTEXT_REG      0x8 /**< DMMU primary context register. */
  62. #define VA_SECONDARY_CONTEXT_REG    0x10    /**< DMMU secondary context register. */
  63. #define VA_DMMU_SFSR            0x18    /**< DMMU sync fault status register. */
  64. #define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
  65. #define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
  66. #define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
  67. #define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
  68. #define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
  69.  
  70. /** I-/D-TLB Data In/Access Register type. */
  71. typedef tte_data_t tlb_data_t;
  72.  
  73. #define tlb_init_arch()
  74.  
  75. #endif
  76.