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/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/** @addtogroup sparc64 
 * @{
 */
/** @file
 */

#ifndef __sparc64_BARRIER_H__
#define __sparc64_BARRIER_H__

/*
 * TODO: Implement true SPARC V9 memory barriers for macros below.
 */
#define CS_ENTER_BARRIER()  __asm__ volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER()  __asm__ volatile ("" ::: "memory")

#define memory_barrier()
#define read_barrier()
#define write_barrier()

/** Flush Instruction Memory instruction. */
static inline void flush(void)
{
    /*
     * The FLUSH instruction takes address parameter.
     * As such, it may trap if the address is not found in DTLB.
     * However, JPS1 implementations are free to ignore the trap.
     */
     
    /*
     * %i7 should provide address that is always mapped in DTLB
     * as it is a pointer to kernel code.
     */
        __asm__ volatile ("flush %i7\n");
}

/** Memory Barrier instruction. */
static inline void membar(void)
{
    __asm__ volatile ("membar #Sync\n");
}

#endif

/** @}
 */