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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __sparc64_ASM_H__
  30. #define __sparc64_ASM_H__
  31.  
  32. #include <arch/types.h>
  33. #include <config.h>
  34.  
  35. /** Enable interrupts.
  36.  *
  37.  * Enable interrupts and return previous
  38.  * value of IPL.
  39.  *
  40.  * @return Old interrupt priority level.
  41.  */
  42. static inline ipl_t interrupts_enable(void) {
  43. }
  44.  
  45. /** Disable interrupts.
  46.  *
  47.  * Disable interrupts and return previous
  48.  * value of IPL.
  49.  *
  50.  * @return Old interrupt priority level.
  51.  */
  52. static inline ipl_t interrupts_disable(void) {
  53. }
  54.  
  55. /** Restore interrupt priority level.
  56.  *
  57.  * Restore IPL.
  58.  *
  59.  * @param ipl Saved interrupt priority level.
  60.  */
  61. static inline void interrupts_restore(ipl_t ipl) {
  62. }
  63.  
  64. /** Return interrupt priority level.
  65.  *
  66.  * Return IPL.
  67.  *
  68.  * @return Current interrupt priority level.
  69.  */
  70. static inline ipl_t interrupts_read(void) {
  71. }
  72.  
  73. /** Return base address of current stack.
  74.  *
  75.  * Return the base address of the current stack.
  76.  * The stack is assumed to be STACK_SIZE bytes long.
  77.  * The stack must start on page boundary.
  78.  */
  79. static inline __address get_stack_base(void)
  80. {
  81.     __address v;
  82.    
  83.     __asm__ volatile ("and %%o6, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
  84.    
  85.     return v;
  86. }
  87.  
  88. /** Read Trap Base Address register.
  89.  *
  90.  * @return Current value in TBA.
  91.  */
  92. static inline __u64 tba_read(void)
  93. {
  94.     __u64 v;
  95.    
  96.     __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
  97.    
  98.     return v;
  99. }
  100.  
  101. /** Write Trap Base Address register.
  102.  *
  103.  * @param New value of TBA.
  104.  */
  105. static inline void tba_write(__u64 v)
  106. {
  107.     __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
  108. }
  109.  
  110. /** Load __u64 from alternate space.
  111.  *
  112.  * @param asi ASI determining the alternate space.
  113.  * @param va Virtual address within the ASI.
  114.  *
  115.  * @return Value read from the virtual address in the specified address space.
  116.  */
  117. static inline __u64 asi_u64_read(asi_t asi, __address va)
  118. {
  119.     __u64 v;
  120.    
  121.     __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
  122.    
  123.     return v;
  124. }
  125.  
  126. /** Store __u64 to alternate space.
  127.  *
  128.  * @param asi ASI determining the alternate space.
  129.  * @param va Virtual address within the ASI.
  130.  * @param v Value to be written.
  131.  */
  132. static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
  133. {
  134.     __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
  135. }
  136.  
  137. void cpu_halt(void);
  138. void cpu_sleep(void);
  139. void asm_delay_loop(__u32 t);
  140.  
  141. #endif
  142.