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  1. /*
  2.  * Copyright (C) 2003-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __mips32_CP0_H__
  30. #define __mips32_CP0_H__
  31.  
  32. #include <arch/types.h>
  33. #include <arch/mm/tlb.h>
  34.  
  35. #define cp0_status_ie_enabled_bit   (1<<0)
  36. #define cp0_status_exl_exception_bit    (1<<1)
  37. #define cp0_status_erl_error_bit    (1<<2)
  38. #define cp0_status_um_bit           (1<<4)
  39. #define cp0_status_bev_bootstrap_bit    (1<<22)
  40. #define cp0_status_fpu_bit              (1<<29)
  41.  
  42. #define cp0_status_im_shift     8
  43. #define cp0_status_im_mask              0xff00
  44.  
  45. #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
  46. #define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
  47.  
  48. #define fpu_cop_id 1
  49.  
  50. /*
  51.  * Magic value for use in msim.
  52.  * On AMD Duron 800Mhz, this roughly seems like one us.
  53.  */
  54. #define cp0_compare_value       10000
  55.  
  56. #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
  57. #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
  58. #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
  59. #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
  60.  
  61. #define GEN_READ_CP0(nm,reg) static inline __u32 cp0_ ##nm##_read(void) \
  62.   { \
  63.       __u32 retval; \
  64.       asm("mfc0 %0, $" #reg : "=r"(retval)); \
  65.       return retval; \
  66.   }
  67.  
  68. #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(__u32 val) \
  69.  { \
  70.     asm("mtc0 %0, $" #reg : : "r"(val) ); \
  71.  }
  72.  
  73. GEN_READ_CP0(index, 0);
  74. GEN_WRITE_CP0(index, 0);
  75.  
  76. GEN_READ_CP0(random, 1);
  77.  
  78. GEN_READ_CP0(entry_lo0, 2);
  79. GEN_WRITE_CP0(entry_lo0, 2);
  80.  
  81. GEN_READ_CP0(entry_lo1, 3);
  82. GEN_WRITE_CP0(entry_lo1, 3);
  83.  
  84. GEN_READ_CP0(context, 4);
  85. GEN_WRITE_CP0(context, 4);
  86.  
  87. GEN_READ_CP0(pagemask, 5);
  88. GEN_WRITE_CP0(pagemask, 5);
  89.  
  90. GEN_READ_CP0(wired, 6);
  91. GEN_WRITE_CP0(wired, 6);
  92.  
  93. GEN_READ_CP0(badvaddr, 8);
  94.  
  95. GEN_READ_CP0(count, 9);
  96. GEN_WRITE_CP0(count, 9);
  97.  
  98. GEN_READ_CP0(entry_hi, 10);
  99. GEN_WRITE_CP0(entry_hi, 10);
  100.  
  101. GEN_READ_CP0(compare, 11);
  102. GEN_WRITE_CP0(compare, 11);
  103.  
  104. GEN_READ_CP0(status, 12);
  105. GEN_WRITE_CP0(status, 12);
  106.  
  107. GEN_READ_CP0(cause, 13);
  108. GEN_WRITE_CP0(cause, 13);
  109.  
  110. GEN_READ_CP0(epc, 14);
  111. GEN_WRITE_CP0(epc, 14);
  112.  
  113. GEN_READ_CP0(prid, 15);
  114.  
  115. #endif
  116.