Subversion Repositories HelenOS-historic

Rev

Rev 912 | Rev 1702 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __ia64_REGISTER_H__
  30. #define __ia64_REGISTER_H__
  31.  
  32. #define CR_IVR_MASK 0xf
  33. #define PSR_IC_MASK 0x2000
  34. #define PSR_I_MASK  0x4000
  35. #define PSR_PK_MASK 0x8000
  36.  
  37. #define PSR_DT_MASK (1<<17)
  38. #define PSR_RT_MASK (1<<27)
  39. #define PSR_IT_MASK 0x0000001000000000
  40.  
  41. #define PSR_CPL_SHIFT       32
  42. #define PSR_CPL_MASK_SHIFTED    3
  43.  
  44. #define PFM_MASK        (~0x3fffffffff)
  45.  
  46. #define RSC_MODE_MASK   3
  47. #define RSC_PL_MASK 12
  48.  
  49. /** Application registers. */
  50. #define AR_KR0      0
  51. #define AR_KR1      1
  52. #define AR_KR2      2
  53. #define AR_KR3      3
  54. #define AR_KR4      4
  55. #define AR_KR5      5
  56. #define AR_KR6      6
  57. #define AR_KR7      7
  58. /* AR 8-15 reserved */
  59. #define AR_RSC      16
  60. #define AR_BSP      17
  61. #define AR_BSPSTORE 18
  62. #define AR_RNAT     19
  63. /* AR 20 reserved */
  64. #define AR_FCR      21
  65. /* AR 22-23 reserved */
  66. #define AR_EFLAG    24
  67. #define AR_CSD      25
  68. #define AR_SSD      26
  69. #define AR_CFLG     27
  70. #define AR_FSR      28
  71. #define AR_FIR      29
  72. #define AR_FDR      30
  73. /* AR 31 reserved */
  74. #define AR_CCV      32
  75. /* AR 33-35 reserved */
  76. #define AR_UNAT     36
  77. /* AR 37-39 reserved */
  78. #define AR_FPSR     40
  79. /* AR 41-43 reserved */
  80. #define AR_ITC      44
  81. /* AR 45-47 reserved */
  82. /* AR 48-63 ignored */
  83. #define AR_PFS      64
  84. #define AR_LC       65
  85. #define AR_EC       66
  86. /* AR 67-111 reserved */
  87. /* AR 112-127 ignored */
  88.  
  89. /** Control registers. */
  90. #define CR_DCR      0
  91. #define CR_ITM      1
  92. #define CR_IVA      2
  93. /* CR3-CR7 reserved */
  94. #define CR_PTA      8
  95. /* CR9-CR15 reserved */
  96. #define CR_IPSR     16
  97. #define CR_ISR      17
  98. /* CR18 reserved */
  99. #define CR_IIP      19
  100. #define CR_IFA      20
  101. #define CR_ITIR     21
  102. #define CR_IIPA     22
  103. #define CR_IFS      23
  104. #define CR_IIM      24
  105. #define CR_IHA      25
  106. /* CR26-CR63 reserved */
  107. #define CR_LID      64
  108. #define CR_IVR      65
  109. #define CR_TPR      66
  110. #define CR_EOI      67
  111. #define CR_IRR0     68
  112. #define CR_IRR1     69
  113. #define CR_IRR2     70
  114. #define CR_IRR3     71
  115. #define CR_ITV      72
  116. #define CR_PMV      73
  117. #define CR_CMCV     74
  118. /* CR75-CR79 reserved */
  119. #define CR_LRR0     80
  120. #define CR_LRR1     81
  121. /* CR82-CR127 reserved */
  122.  
  123. #ifndef __ASM__
  124.  
  125. #include <arch/types.h>
  126.  
  127. /** Processor Status Register. */
  128. union psr {
  129.     __u64 value;
  130.     struct {
  131.         unsigned : 1;
  132.         unsigned be : 1;    /**< Big-Endian data accesses. */
  133.         unsigned up : 1;    /**< User Performance monitor enable. */
  134.         unsigned ac : 1;    /**< Alignment Check. */
  135.         unsigned mfl : 1;   /**< Lower floating-point register written. */
  136.         unsigned mfh : 1;   /**< Upper floating-point register written. */
  137.         unsigned : 7;
  138.         unsigned ic : 1;    /**< Interruption Collection. */
  139.         unsigned i : 1;     /**< Interrupt Bit. */
  140.         unsigned pk : 1;    /**< Protection Key enable. */
  141.         unsigned : 1;
  142.         unsigned dt : 1;    /**< Data address Translation. */
  143.         unsigned dfl : 1;   /**< Disabled Floating-point Low register set. */
  144.         unsigned dfh : 1;   /**< Disabled Floating-point High register set. */
  145.         unsigned sp : 1;    /**< Secure Performance monitors. */
  146.         unsigned pp : 1;    /**< Privileged Performance monitor enable. */
  147.         unsigned di : 1;    /**< Disable Instruction set transition. */
  148.         unsigned si : 1;    /**< Secure Interval timer. */
  149.         unsigned db : 1;    /**< Debug Breakpoint fault. */
  150.         unsigned lp : 1;    /**< Lower Privilege transfer trap. */
  151.         unsigned tb : 1;    /**< Taken Branch trap. */
  152.         unsigned rt : 1;    /**< Register Stack Translation. */
  153.         unsigned : 4;
  154.         unsigned cpl : 2;   /**< Current Privilege Level. */
  155.         unsigned is : 1;    /**< Instruction Set. */
  156.         unsigned mc : 1;    /**< Machine Check abort mask. */
  157.         unsigned it : 1;    /**< Instruction address Translation. */
  158.         unsigned id : 1;    /**< Instruction Debug fault disable. */
  159.         unsigned da : 1;    /**< Disable Data Access and Dirty-bit faults. */
  160.         unsigned dd : 1;    /**< Data Debug fault disable. */
  161.         unsigned ss : 1;    /**< Single Step enable. */
  162.         unsigned ri : 2;    /**< Restart Instruction. */
  163.         unsigned ed : 1;    /**< Exception Deferral. */
  164.         unsigned bn : 1;    /**< Register Bank. */
  165.         unsigned ia : 1;    /**< Disable Instruction Access-bit faults. */
  166.     } __attribute__ ((packed));
  167. };
  168. typedef union psr psr_t;
  169.  
  170. /** Register Stack Configuration Register */
  171. union rsc {
  172.     __u64 value;
  173.     struct {
  174.         unsigned mode : 2;
  175.         unsigned pl : 2;    /**< Privilege Level. */
  176.         unsigned be : 1;    /**< Big-endian. */
  177.         unsigned : 11;
  178.         unsigned loadrs : 14;
  179.     } __attribute__ ((packed));
  180. };
  181. typedef union rsc rsc_t;
  182.  
  183. /** External Interrupt Vector Register */
  184. union cr_ivr {
  185.     __u8  vector;
  186.     __u64 value;
  187. };
  188.  
  189. typedef union cr_ivr cr_ivr_t;
  190.  
  191. /** Task Priority Register */
  192. union cr_tpr {
  193.     struct {
  194.         unsigned : 4;
  195.         unsigned mic: 4;        /**< Mask Interrupt Class. */
  196.         unsigned : 8;
  197.         unsigned mmi: 1;        /**< Mask Maskable Interrupts. */
  198.     } __attribute__ ((packed));
  199.     __u64 value;
  200. };
  201.  
  202. typedef union cr_tpr cr_tpr_t;
  203.  
  204. /** Interval Timer Vector */
  205. union cr_itv {
  206.     struct {
  207.         unsigned vector : 8;
  208.         unsigned : 4;
  209.         unsigned : 1;
  210.         unsigned : 3;
  211.         unsigned m : 1;         /**< Mask. */
  212.     } __attribute__ ((packed));
  213.     __u64 value;
  214. };
  215.  
  216. typedef union cr_itv cr_itv_t;
  217.  
  218. /** Interruption Status Register */
  219. union cr_isr {
  220.     struct {
  221.         union {
  222.             /** General Exception code field structuring. */
  223.             struct {
  224.                 unsigned ge_na : 4;
  225.                 unsigned ge_code : 4;
  226.             } __attribute__ ((packed));
  227.             __u16 code;
  228.         };
  229.         __u8 vector;
  230.         unsigned : 8;
  231.         unsigned x : 1;         /**< Execute exception. */
  232.         unsigned w : 1;         /**< Write exception. */
  233.         unsigned r : 1;         /**< Read exception. */
  234.         unsigned na : 1;        /**< Non-access exception. */
  235.         unsigned sp : 1;        /**< Speculative load exception. */
  236.         unsigned rs : 1;        /**< Register stack. */
  237.         unsigned ir : 1;        /**< Incomplete Register frame. */
  238.         unsigned ni : 1;        /**< Nested Interruption. */
  239.         unsigned so : 1;        /**< IA-32 Supervisor Override. */
  240.         unsigned ei : 2;        /**< Excepting Instruction. */
  241.         unsigned ed : 1;        /**< Exception Deferral. */
  242.         unsigned : 20;
  243.     } __attribute__ ((packed));
  244.     __u64 value;
  245. };
  246.  
  247. typedef union cr_isr cr_isr_t;
  248.  
  249. /** CPUID Register 3 */
  250. union cpuid3 {
  251.     struct {
  252.         __u8 number;
  253.         __u8 revision;
  254.         __u8 model;
  255.         __u8 family;
  256.         __u8 archrev;
  257.     } __attribute__ ((packed));
  258.     __u64 value;
  259. };
  260.  
  261. typedef union cpuid3 cpuid3_t;
  262.  
  263. #endif /* !__ASM__ */
  264.  
  265. #endif
  266.