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  1. /*
  2.  * Copyright (c) 2006 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_sparc64_Z8530_H_
  36. #define KERN_sparc64_Z8530_H_
  37.  
  38. #include <arch/types.h>
  39. #include <arch/drivers/kbd.h>
  40.  
  41. #define Z8530_CHAN_A    4
  42. #define Z8530_CHAN_B    0
  43.  
  44. #define WR0 0
  45. #define WR1 1
  46. #define WR2 2
  47. #define WR3 3
  48. #define WR4 4
  49. #define WR5 5
  50. #define WR6 6
  51. #define WR7 7
  52. #define WR8 8
  53. #define WR9 9
  54. #define WR10    10
  55. #define WR11    11
  56. #define WR12    12
  57. #define WR13    13
  58. #define WR14    14
  59. #define WR15    15
  60.  
  61. #define RR0 0
  62. #define RR1 1
  63. #define RR2 2
  64. #define RR3 3
  65. #define RR8 8
  66. #define RR10    10
  67. #define RR12    12
  68. #define RR13    13
  69. #define RR14    14
  70. #define RR15    15
  71.  
  72. /* Write Register 0 */
  73. #define WR0_TX_IP_RST   (0x5<<3)    /** Reset pending TX interrupt. */
  74. #define WR0_ERR_RST (0x6<<3)
  75.  
  76. /* Write Register 1 */
  77. #define WR1_RID     (0x0<<3)    /** Receive Interrupts Disabled. */
  78. #define WR1_RIFCSC  (0x1<<3)    /** Receive Interrupt on First Character or Special Condition. */
  79. #define WR1_IARCSC  (0x2<<3)    /** Interrupt on All Receive Characters or Special Conditions. */
  80. #define WR1_RISC    (0x3<<3)    /** Receive Interrupt on Special Condition. */
  81. #define WR1_PISC    (0x1<<2)    /** Parity Is Special Condition. */
  82.  
  83. /* Write Register 3 */
  84. #define WR3_RX_ENABLE   (0x1<<0)    /** Rx Enable. */
  85. #define WR3_RX8BITSCH   (0x3<<6)    /** 8-bits per character. */
  86.  
  87. /* Write Register 9 */
  88. #define WR9_MIE     (0x1<<3)    /** Master Interrupt Enable. */
  89.  
  90. /* Read Register 0 */
  91. #define RR0_RCA     (0x1<<0)    /** Receive Character Available. */
  92.  
  93. /** Structure representing the z8530 device. */
  94. typedef struct {
  95.     devno_t devno;
  96.     volatile uint8_t *reg;      /** Memory mapped registers of the z8530. */
  97. } z8530_t;
  98.  
  99. static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val)
  100. {
  101.     /*
  102.      * Registers 8-15 will automatically issue the Point High
  103.      * command as their bit 3 is 1.
  104.      */
  105.     dev->reg[WR0+chan] = reg;   /* select register */
  106.     dev->reg[WR0+chan] = val;   /* write value */
  107. }
  108.  
  109. static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val)
  110. {
  111.     z8530_write(dev, Z8530_CHAN_A, reg, val);
  112. }
  113. static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val)
  114. {
  115.     z8530_write(dev, Z8530_CHAN_B, reg, val);
  116. }
  117.  
  118. static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg)
  119. {
  120.     /*
  121.      * Registers 8-15 will automatically issue the Point High
  122.      * command as their bit 3 is 1.
  123.      */
  124.     dev->reg[WR0+chan] = reg;   /* select register */
  125.     return dev->reg[WR0+chan];
  126. }
  127.  
  128. static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg)
  129. {
  130.     return z8530_read(dev, Z8530_CHAN_A, reg);
  131. }
  132. static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg)
  133. {
  134.     return z8530_read(dev, Z8530_CHAN_B, reg);
  135. }
  136.  
  137. #endif
  138.  
  139. /** @}
  140.  */
  141.