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  1. /*
  2.  * Copyright (c) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/drivers/tick.h>
  36. #include <arch/interrupt.h>
  37. #include <arch/sparc64.h>
  38. #include <arch/asm.h>
  39. #include <arch/register.h>
  40. #include <arch/cpu.h>
  41. #include <arch/boot/boot.h>
  42. #include <time/clock.h>
  43. #include <arch.h>
  44. #include <debug.h>
  45.  
  46. #define TICK_RESTART_TIME   50  /* Worst case estimate. */
  47.  
  48. /** Initialize tick interrupt. */
  49. void tick_init(void)
  50. {
  51.     tick_compare_reg_t compare;
  52.    
  53.     interrupt_register(14, "tick_int", tick_interrupt);
  54.     compare.int_dis = false;
  55.     compare.tick_cmpr = CPU->arch.clock_frequency / HZ;
  56.     CPU->arch.next_tick_cmpr = compare.tick_cmpr;
  57.     tick_compare_write(compare.value);
  58.     tick_write(0);
  59. }
  60.  
  61. /** Process tick interrupt.
  62.  *
  63.  * @param n Interrupt Level, 14,  (can be ignored)
  64.  * @param istate Interrupted state.
  65.  */
  66. void tick_interrupt(int n, istate_t *istate)
  67. {
  68.     softint_reg_t softint, clear;
  69.     uint64_t drift;
  70.    
  71.     softint.value = softint_read();
  72.    
  73.     /*
  74.      * Make sure we are servicing interrupt_level_14
  75.      */
  76.     ASSERT(n == 14);
  77.    
  78.     /*
  79.      * Make sure we are servicing TICK_INT.
  80.      */
  81.     ASSERT(softint.tick_int);
  82.  
  83.     /*
  84.      * Clear tick interrupt.
  85.      */
  86.     clear.value = 0;
  87.     clear.tick_int = 1;
  88.     clear_softint_write(clear.value);
  89.    
  90.     /*
  91.      * Reprogram the compare register.
  92.      * For now, we can ignore the potential of the registers to overflow.
  93.      * On a 360MHz Ultra 60, the 63-bit compare counter will overflow in
  94.      * about 812 years. If there was a 2GHz UltraSPARC computer, it would
  95.      * overflow only in 146 years.
  96.      */
  97.     drift = tick_read() - CPU->arch.next_tick_cmpr;
  98.     while (drift > CPU->arch.clock_frequency / HZ) {
  99.         drift -= CPU->arch.clock_frequency / HZ;
  100.         CPU->missed_clock_ticks++;
  101.     }
  102.     CPU->arch.next_tick_cmpr = tick_read() +
  103.         (CPU->arch.clock_frequency / HZ) - drift;
  104.     tick_compare_write(CPU->arch.next_tick_cmpr);
  105.     clock();
  106. }
  107.  
  108. /** @}
  109.  */
  110.