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  1. /*
  2.  * Copyright (c) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup ia64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_ia64_CPU_H_
  36. #define KERN_ia64_CPU_H_
  37.  
  38. #include <arch/types.h>
  39. #include <arch/register.h>
  40. #include <arch/asm.h>
  41. #include <arch/bootinfo.h>
  42.  
  43. #define FAMILY_ITANIUM  0x7
  44. #define FAMILY_ITANIUM2 0x1f
  45.  
  46. typedef struct {
  47.     uint64_t cpuid0;
  48.     uint64_t cpuid1;
  49.     cpuid3_t cpuid3;
  50. } cpu_arch_t;
  51.  
  52. /** Read CPUID register.
  53.  *
  54.  * @param n CPUID register number.
  55.  *
  56.  * @return Value of CPUID[n] register.
  57.  */
  58. static inline uint64_t cpuid_read(int n)
  59. {
  60.     uint64_t v;
  61.    
  62.     asm volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n));
  63.    
  64.     return v;
  65. }
  66.  
  67.  
  68. #define CR64_ID_SHIFT 24
  69. #define CR64_ID_MASK 0xff000000
  70. #define CR64_EID_SHIFT 16
  71. #define CR64_EID_MASK 0xff0000
  72.  
  73. static inline int ia64_get_cpu_id(void)
  74. {
  75.     uint64_t cr64=cr64_read();
  76.     return ((CR64_ID_MASK)&cr64)>>CR64_ID_SHIFT;
  77. }
  78.  
  79. static inline int ia64_get_cpu_eid(void)
  80. {
  81.     uint64_t cr64=cr64_read();
  82.     return ((CR64_EID_MASK)&cr64)>>CR64_EID_SHIFT;
  83. }
  84.  
  85.  
  86. static inline void ipi_send_ipi(int id, int eid, int intno)
  87. {
  88.     (bootinfo->sapic)[2 * (id * 256 + eid)] = intno;
  89.     srlz_d();
  90.  
  91. }
  92.  
  93. #endif
  94.  
  95. /** @}
  96.  */
  97.