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  1. /*
  2.  * Copyright (c) 2003-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup mips32mm
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/mm/tlb.h>
  36. #include <mm/asid.h>
  37. #include <mm/tlb.h>
  38. #include <mm/page.h>
  39. #include <mm/as.h>
  40. #include <arch/cp0.h>
  41. #include <panic.h>
  42. #include <arch.h>
  43. #include <synch/mutex.h>
  44. #include <print.h>
  45. #include <debug.h>
  46. #include <align.h>
  47. #include <interrupt.h>
  48. #include <symtab.h>
  49.  
  50. static void tlb_refill_fail(istate_t *);
  51. static void tlb_invalid_fail(istate_t *);
  52. static void tlb_modified_fail(istate_t *);
  53.  
  54. static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *);
  55.  
  56. /** Initialize TLB.
  57.  *
  58.  * Invalidate all entries and mark wired entries.
  59.  */
  60. void tlb_arch_init(void)
  61. {
  62.     int i;
  63.  
  64.     cp0_pagemask_write(TLB_PAGE_MASK_16K);
  65.     cp0_entry_hi_write(0);
  66.     cp0_entry_lo0_write(0);
  67.     cp0_entry_lo1_write(0);
  68.  
  69.     /* Clear and initialize TLB. */
  70.    
  71.     for (i = 0; i < TLB_ENTRY_COUNT; i++) {
  72.         cp0_index_write(i);
  73.         tlbwi();
  74.     }
  75.        
  76.     /*
  77.      * The kernel is going to make use of some wired
  78.      * entries (e.g. mapping kernel stacks in kseg3).
  79.      */
  80.     cp0_wired_write(TLB_WIRED);
  81. }
  82.  
  83. /** Process TLB Refill Exception.
  84.  *
  85.  * @param istate    Interrupted register context.
  86.  */
  87. void tlb_refill(istate_t *istate)
  88. {
  89.     entry_lo_t lo;
  90.     entry_hi_t hi;
  91.     asid_t asid;
  92.     uintptr_t badvaddr;
  93.     pte_t *pte;
  94.     int pfrc;
  95.    
  96.     badvaddr = cp0_badvaddr_read();
  97.    
  98.     mutex_lock(&AS->lock);
  99.     asid = AS->asid;
  100.     mutex_unlock(&AS->lock);
  101.    
  102.     page_table_lock(AS, true);
  103.    
  104.     pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
  105.     if (!pte) {
  106.         switch (pfrc) {
  107.         case AS_PF_FAULT:
  108.             goto fail;
  109.             break;
  110.         case AS_PF_DEFER:
  111.             /*
  112.              * The page fault came during copy_from_uspace()
  113.              * or copy_to_uspace().
  114.              */
  115.             page_table_unlock(AS, true);
  116.             return;
  117.         default:
  118.             panic("Unexpected pfrc (%d).", pfrc);
  119.         }
  120.     }
  121.  
  122.     /*
  123.      * Record access to PTE.
  124.      */
  125.     pte->a = 1;
  126.  
  127.     tlb_prepare_entry_hi(&hi, asid, badvaddr);
  128.     tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
  129.         pte->pfn);
  130.  
  131.     /*
  132.      * New entry is to be inserted into TLB
  133.      */
  134.     cp0_entry_hi_write(hi.value);
  135.     if ((badvaddr / PAGE_SIZE) % 2 == 0) {
  136.         cp0_entry_lo0_write(lo.value);
  137.         cp0_entry_lo1_write(0);
  138.     }
  139.     else {
  140.         cp0_entry_lo0_write(0);
  141.         cp0_entry_lo1_write(lo.value);
  142.     }
  143.     cp0_pagemask_write(TLB_PAGE_MASK_16K);
  144.     tlbwr();
  145.  
  146.     page_table_unlock(AS, true);
  147.     return;
  148.    
  149. fail:
  150.     page_table_unlock(AS, true);
  151.     tlb_refill_fail(istate);
  152. }
  153.  
  154. /** Process TLB Invalid Exception.
  155.  *
  156.  * @param istate    Interrupted register context.
  157.  */
  158. void tlb_invalid(istate_t *istate)
  159. {
  160.     tlb_index_t index;
  161.     uintptr_t badvaddr;
  162.     entry_lo_t lo;
  163.     entry_hi_t hi;
  164.     pte_t *pte;
  165.     int pfrc;
  166.  
  167.     badvaddr = cp0_badvaddr_read();
  168.  
  169.     /*
  170.      * Locate the faulting entry in TLB.
  171.      */
  172.     hi.value = cp0_entry_hi_read();
  173.     tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
  174.     cp0_entry_hi_write(hi.value);
  175.     tlbp();
  176.     index.value = cp0_index_read();
  177.  
  178.     page_table_lock(AS, true); 
  179.    
  180.     /*
  181.      * Fail if the entry is not in TLB.
  182.      */
  183.     if (index.p) {
  184.         printf("TLB entry not found.\n");
  185.         goto fail;
  186.     }
  187.  
  188.     pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
  189.     if (!pte) {
  190.         switch (pfrc) {
  191.         case AS_PF_FAULT:
  192.             goto fail;
  193.             break;
  194.         case AS_PF_DEFER:
  195.             /*
  196.              * The page fault came during copy_from_uspace()
  197.              * or copy_to_uspace().
  198.              */
  199.             page_table_unlock(AS, true);             
  200.             return;
  201.         default:
  202.             panic("Unexpected pfrc (%d).", pfrc);
  203.         }
  204.     }
  205.  
  206.     /*
  207.      * Read the faulting TLB entry.
  208.      */
  209.     tlbr();
  210.  
  211.     /*
  212.      * Record access to PTE.
  213.      */
  214.     pte->a = 1;
  215.  
  216.     tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
  217.         pte->pfn);
  218.  
  219.     /*
  220.      * The entry is to be updated in TLB.
  221.      */
  222.     if ((badvaddr / PAGE_SIZE) % 2 == 0)
  223.         cp0_entry_lo0_write(lo.value);
  224.     else
  225.         cp0_entry_lo1_write(lo.value);
  226.     cp0_pagemask_write(TLB_PAGE_MASK_16K);
  227.     tlbwi();
  228.  
  229.     page_table_unlock(AS, true);
  230.     return;
  231.    
  232. fail:
  233.     page_table_unlock(AS, true);
  234.     tlb_invalid_fail(istate);
  235. }
  236.  
  237. /** Process TLB Modified Exception.
  238.  *
  239.  * @param istate    Interrupted register context.
  240.  */
  241. void tlb_modified(istate_t *istate)
  242. {
  243.     tlb_index_t index;
  244.     uintptr_t badvaddr;
  245.     entry_lo_t lo;
  246.     entry_hi_t hi;
  247.     pte_t *pte;
  248.     int pfrc;
  249.  
  250.     badvaddr = cp0_badvaddr_read();
  251.  
  252.     /*
  253.      * Locate the faulting entry in TLB.
  254.      */
  255.     hi.value = cp0_entry_hi_read();
  256.     tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
  257.     cp0_entry_hi_write(hi.value);
  258.     tlbp();
  259.     index.value = cp0_index_read();
  260.  
  261.     page_table_lock(AS, true); 
  262.    
  263.     /*
  264.      * Fail if the entry is not in TLB.
  265.      */
  266.     if (index.p) {
  267.         printf("TLB entry not found.\n");
  268.         goto fail;
  269.     }
  270.  
  271.     pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
  272.     if (!pte) {
  273.         switch (pfrc) {
  274.         case AS_PF_FAULT:
  275.             goto fail;
  276.             break;
  277.         case AS_PF_DEFER:
  278.             /*
  279.              * The page fault came during copy_from_uspace()
  280.              * or copy_to_uspace().
  281.              */
  282.             page_table_unlock(AS, true);             
  283.             return;
  284.         default:
  285.             panic("Unexpected pfrc (%d).", pfrc);
  286.         }
  287.     }
  288.  
  289.     /*
  290.      * Read the faulting TLB entry.
  291.      */
  292.     tlbr();
  293.  
  294.     /*
  295.      * Record access and write to PTE.
  296.      */
  297.     pte->a = 1;
  298.     pte->d = 1;
  299.  
  300.     tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
  301.         pte->pfn);
  302.  
  303.     /*
  304.      * The entry is to be updated in TLB.
  305.      */
  306.     if ((badvaddr / PAGE_SIZE) % 2 == 0)
  307.         cp0_entry_lo0_write(lo.value);
  308.     else
  309.         cp0_entry_lo1_write(lo.value);
  310.     cp0_pagemask_write(TLB_PAGE_MASK_16K);
  311.     tlbwi();
  312.  
  313.     page_table_unlock(AS, true);
  314.     return;
  315.    
  316. fail:
  317.     page_table_unlock(AS, true);
  318.     tlb_modified_fail(istate);
  319. }
  320.  
  321. void tlb_refill_fail(istate_t *istate)
  322. {
  323.     char *symbol, *sym2;
  324.  
  325.     symbol = symtab_fmt_name_lookup(istate->epc);
  326.     sym2 = symtab_fmt_name_lookup(istate->ra);
  327.    
  328.     fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
  329.         cp0_badvaddr_read());
  330.     panic("%x: TLB Refill Exception at %x (%s<-%s).", cp0_badvaddr_read(),
  331.         istate->epc, symbol, sym2);
  332. }
  333.  
  334.  
  335. void tlb_invalid_fail(istate_t *istate)
  336. {
  337.     char *symbol;
  338.  
  339.     symbol = symtab_fmt_name_lookup(istate->epc);
  340.  
  341.     fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
  342.         cp0_badvaddr_read());
  343.     panic("%x: TLB Invalid Exception at %x (%s).", cp0_badvaddr_read(),
  344.         istate->epc, symbol);
  345. }
  346.  
  347. void tlb_modified_fail(istate_t *istate)
  348. {
  349.     char *symbol;
  350.  
  351.     symbol = symtab_fmt_name_lookup(istate->epc);
  352.  
  353.     fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
  354.         cp0_badvaddr_read());
  355.     panic("%x: TLB Modified Exception at %x (%s).", cp0_badvaddr_read(),
  356.         istate->epc, symbol);
  357. }
  358.  
  359. /** Try to find PTE for faulting address.
  360.  *
  361.  * The AS->lock must be held on entry to this function.
  362.  *
  363.  * @param badvaddr  Faulting virtual address.
  364.  * @param access    Access mode that caused the fault.
  365.  * @param istate    Pointer to interrupted state.
  366.  * @param pfrc      Pointer to variable where as_page_fault() return code
  367.  *          will be stored.
  368.  *
  369.  * @return      PTE on success, NULL otherwise.
  370.  */
  371. pte_t *
  372. find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
  373.     int *pfrc)
  374. {
  375.     entry_hi_t hi;
  376.     pte_t *pte;
  377.  
  378.     hi.value = cp0_entry_hi_read();
  379.  
  380.     /*
  381.      * Handler cannot succeed if the ASIDs don't match.
  382.      */
  383.     if (hi.asid != AS->asid) {
  384.         printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
  385.         return NULL;
  386.     }
  387.  
  388.     /*
  389.      * Check if the mapping exists in page tables.
  390.      */
  391.     pte = page_mapping_find(AS, badvaddr);
  392.     if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) {
  393.         /*
  394.          * Mapping found in page tables.
  395.          * Immediately succeed.
  396.          */
  397.         return pte;
  398.     } else {
  399.         int rc;
  400.        
  401.         /*
  402.          * Mapping not found in page tables.
  403.          * Resort to higher-level page fault handler.
  404.          */
  405.         page_table_unlock(AS, true);
  406.         switch (rc = as_page_fault(badvaddr, access, istate)) {
  407.         case AS_PF_OK:
  408.             /*
  409.              * The higher-level page fault handler succeeded,
  410.              * The mapping ought to be in place.
  411.              */
  412.             page_table_lock(AS, true);
  413.             pte = page_mapping_find(AS, badvaddr);
  414.             ASSERT(pte && pte->p);
  415.             ASSERT(pte->w || access != PF_ACCESS_WRITE);
  416.             return pte;
  417.             break;
  418.         case AS_PF_DEFER:
  419.             page_table_lock(AS, true);
  420.             *pfrc = AS_PF_DEFER;
  421.             return NULL;
  422.             break;
  423.         case AS_PF_FAULT:
  424.             page_table_lock(AS, true);
  425.             *pfrc = AS_PF_FAULT;
  426.             return NULL;
  427.             break;
  428.         default:
  429.             panic("Unexpected rc (%d).", rc);
  430.         }
  431.        
  432.     }
  433. }
  434.  
  435. void
  436. tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
  437.     uintptr_t pfn)
  438. {
  439.     lo->value = 0;
  440.     lo->g = g;
  441.     lo->v = v;
  442.     lo->d = d;
  443.     lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
  444.     lo->pfn = pfn;
  445. }
  446.  
  447. void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
  448. {
  449.     hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
  450.     hi->asid = asid;
  451. }
  452.  
  453. /** Print contents of TLB. */
  454. void tlb_print(void)
  455. {
  456.     page_mask_t mask;
  457.     entry_lo_t lo0, lo1;
  458.     entry_hi_t hi, hi_save;
  459.     unsigned int i;
  460.  
  461.     hi_save.value = cp0_entry_hi_read();
  462.    
  463.     printf("#  ASID VPN2   MASK G V D C PFN\n");
  464.     printf("-- ---- ------ ---- - - - - ------\n");
  465.    
  466.     for (i = 0; i < TLB_ENTRY_COUNT; i++) {
  467.         cp0_index_write(i);
  468.         tlbr();
  469.        
  470.         mask.value = cp0_pagemask_read();
  471.         hi.value = cp0_entry_hi_read();
  472.         lo0.value = cp0_entry_lo0_read();
  473.         lo1.value = cp0_entry_lo1_read();
  474.        
  475.         printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",
  476.             i, hi.asid, hi.vpn2, mask.mask,
  477.             lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
  478.         printf("                    %1u %1u %1u %1u %#6x\n",
  479.             lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
  480.     }
  481.    
  482.     cp0_entry_hi_write(hi_save.value);
  483. }
  484.  
  485. /** Invalidate all not wired TLB entries. */
  486. void tlb_invalidate_all(void)
  487. {
  488.     ipl_t ipl;
  489.     entry_lo_t lo0, lo1;
  490.     entry_hi_t hi_save;
  491.     int i;
  492.  
  493.     hi_save.value = cp0_entry_hi_read();
  494.     ipl = interrupts_disable();
  495.  
  496.     for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
  497.         cp0_index_write(i);
  498.         tlbr();
  499.  
  500.         lo0.value = cp0_entry_lo0_read();
  501.         lo1.value = cp0_entry_lo1_read();
  502.  
  503.         lo0.v = 0;
  504.         lo1.v = 0;
  505.  
  506.         cp0_entry_lo0_write(lo0.value);
  507.         cp0_entry_lo1_write(lo1.value);
  508.                
  509.         tlbwi();
  510.     }
  511.    
  512.     interrupts_restore(ipl);
  513.     cp0_entry_hi_write(hi_save.value);
  514. }
  515.  
  516. /** Invalidate all TLB entries belonging to specified address space.
  517.  *
  518.  * @param asid Address space identifier.
  519.  */
  520. void tlb_invalidate_asid(asid_t asid)
  521. {
  522.     ipl_t ipl;
  523.     entry_lo_t lo0, lo1;
  524.     entry_hi_t hi, hi_save;
  525.     int i;
  526.  
  527.     ASSERT(asid != ASID_INVALID);
  528.  
  529.     hi_save.value = cp0_entry_hi_read();
  530.     ipl = interrupts_disable();
  531.    
  532.     for (i = 0; i < TLB_ENTRY_COUNT; i++) {
  533.         cp0_index_write(i);
  534.         tlbr();
  535.        
  536.         hi.value = cp0_entry_hi_read();
  537.        
  538.         if (hi.asid == asid) {
  539.             lo0.value = cp0_entry_lo0_read();
  540.             lo1.value = cp0_entry_lo1_read();
  541.  
  542.             lo0.v = 0;
  543.             lo1.v = 0;
  544.  
  545.             cp0_entry_lo0_write(lo0.value);
  546.             cp0_entry_lo1_write(lo1.value);
  547.  
  548.             tlbwi();
  549.         }
  550.     }
  551.    
  552.     interrupts_restore(ipl);
  553.     cp0_entry_hi_write(hi_save.value);
  554. }
  555.  
  556. /** Invalidate TLB entries for specified page range belonging to specified
  557.  * address space.
  558.  *
  559.  * @param asid      Address space identifier.
  560.  * @param page      First page whose TLB entry is to be invalidated.
  561.  * @param cnt       Number of entries to invalidate.
  562.  */
  563. void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
  564. {
  565.     unsigned int i;
  566.     ipl_t ipl;
  567.     entry_lo_t lo0, lo1;
  568.     entry_hi_t hi, hi_save;
  569.     tlb_index_t index;
  570.  
  571.     ASSERT(asid != ASID_INVALID);
  572.  
  573.     hi_save.value = cp0_entry_hi_read();
  574.     ipl = interrupts_disable();
  575.  
  576.     for (i = 0; i < cnt + 1; i += 2) {
  577.         hi.value = 0;
  578.         tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
  579.         cp0_entry_hi_write(hi.value);
  580.  
  581.         tlbp();
  582.         index.value = cp0_index_read();
  583.  
  584.         if (!index.p) {
  585.             /*
  586.              * Entry was found, index register contains valid
  587.              * index.
  588.              */
  589.             tlbr();
  590.  
  591.             lo0.value = cp0_entry_lo0_read();
  592.             lo1.value = cp0_entry_lo1_read();
  593.  
  594.             lo0.v = 0;
  595.             lo1.v = 0;
  596.  
  597.             cp0_entry_lo0_write(lo0.value);
  598.             cp0_entry_lo1_write(lo1.value);
  599.  
  600.             tlbwi();
  601.         }
  602.     }
  603.    
  604.     interrupts_restore(ipl);
  605.     cp0_entry_hi_write(hi_save.value);
  606. }
  607.  
  608. /** @}
  609.  */
  610.