/*
* Copyright (c) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup arm32mm
* @{
*/
/** @file
*/
#include "mm.h"
/** Set page table entry to point no frame, be read/write by kernel,
* no access by user, become to domain 0, no cache or buffer
* \param pte page table entry to set
* \param frame frame number of first frame 1MB section
* Note: If frame not aligned it's used first lower 1MB aligned frame
*/
static void init_pte_level0_section_entry( pte_level0_section* pte, unsigned frame){
pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
pte->bufferable = 0; // disable
pte->cacheable = 0;
pte->machine_depend = 0;
pte->domain = 0;
pte->should_be_zero_1 = 0;
pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
pte->should_be_zero_2 = 0;
pte->section_base_addr = (frame << FRAME_WIDTH) >> 20;
};
void mm_kernel_mapping(void) {
int i;
// Create 1:1 mapping
for( i=0; i < PTL0_ENTRIES_ARCH; i++) {
init_pte_level0_section_entry(&page_table[i], i * FRAMES_PER_SECTION);
}
// Create kernel mapping
const unsigned int offset = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION;
for( i = offset; i < PTL0_ENTRIES_ARCH; i++) {
init_pte_level0_section_entry(&page_table[i], (i - offset) * FRAMES_PER_SECTION);
}
SET_PTL0_ADDRESS_ARCH( page_table);
// Enable paging
asm volatile (
"ldr r0, =0x55555555 \n"
"mcr p15, 0, r0, c3, c0, 0 \n" // Set domain acces rights to client <==> take rights from page tables
"mrc p15, 0, r0, c1, c0, 0 \n" // Get current setting of system ... register 1 isn't only for memmory management
"ldr r1, =0xFFFFFE8D \n" // Mask to disable aligment checks; system & rom bit disable
"and r0, r0, r1 \n"
"ldr r1, =0x00000001 \n" // Mask to enable paging
"orr r0, r0, r1 \n"
"mcr p15, 0, r0, c1, c0, 0 \n" // Store setting
:
:
: "r0", "r1"
);
};
/** @}
*/