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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29.  /** @addtogroup sparc64mm 
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/mm/tlb.h>
  36. #include <mm/tlb.h>
  37. #include <arch/mm/frame.h>
  38. #include <arch/mm/page.h>
  39. #include <arch/mm/mmu.h>
  40. #include <mm/asid.h>
  41. #include <print.h>
  42. #include <arch/types.h>
  43. #include <typedefs.h>
  44. #include <config.h>
  45. #include <arch/trap/trap.h>
  46. #include <panic.h>
  47. #include <arch/asm.h>
  48. #include <symtab.h>
  49.  
  50. #include <arch/drivers/fb.h>
  51. #include <arch/drivers/i8042.h>
  52.  
  53. char *context_encoding[] = {
  54.     "Primary",
  55.     "Secondary",
  56.     "Nucleus",
  57.     "Reserved"
  58. };
  59.  
  60. /** Initialize ITLB and DTLB.
  61.  *
  62.  * The goal of this function is to disable MMU
  63.  * so that both TLBs can be purged and new
  64.  * kernel 4M locked entry can be installed.
  65.  * After TLB is initialized, MMU is enabled
  66.  * again.
  67.  *
  68.  * Switching MMU off imposes the requirement for
  69.  * the kernel to run in identity mapped environment.
  70.  */
  71. void tlb_arch_init(void)
  72. {
  73.     tlb_tag_access_reg_t tag;
  74.     tlb_data_t data;
  75.     frame_address_t fr;
  76.     page_address_t pg;
  77.  
  78.     fr.address = config.base;
  79.     pg.address = config.base;
  80.  
  81.     immu_disable();
  82.     dmmu_disable();
  83.  
  84.     /*
  85.      * Demap everything, especially OpenFirmware.
  86.      */
  87.     itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  88.     dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  89.    
  90.     /*
  91.      * We do identity mapping of 4M-page at 4M.
  92.      */
  93.     tag.value = ASID_KERNEL;
  94.     tag.vpn = pg.vpn;
  95.  
  96.     itlb_tag_access_write(tag.value);
  97.     dtlb_tag_access_write(tag.value);
  98.  
  99.     data.value = 0;
  100.     data.v = true;
  101.     data.size = PAGESIZE_4M;
  102.     data.pfn = fr.pfn;
  103.     data.l = true;
  104.     data.cp = 1;
  105.     data.cv = 1;
  106.     data.p = true;
  107.     data.w = true;
  108.     data.g = true;
  109.  
  110.     itlb_data_in_write(data.value);
  111.     dtlb_data_in_write(data.value);
  112.  
  113.     /*
  114.      * Register window traps can occur before MMU is enabled again.
  115.      * This ensures that any such traps will be handled from
  116.      * kernel identity mapped trap handler.
  117.      */
  118.     trap_switch_trap_table();
  119.    
  120.     tlb_invalidate_all();
  121.  
  122.     dmmu_enable();
  123.     immu_enable();
  124. }
  125.  
  126. /** Insert privileged mapping into DMMU TLB.
  127.  *
  128.  * @param page Virtual page address.
  129.  * @param frame Physical frame address.
  130.  * @param pagesize Page size.
  131.  * @param locked True for permanent mappings, false otherwise.
  132.  * @param cacheable True if the mapping is cacheable, false otherwise.
  133.  */
  134. void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
  135. {
  136.     tlb_tag_access_reg_t tag;
  137.     tlb_data_t data;
  138.     page_address_t pg;
  139.     frame_address_t fr;
  140.  
  141.     pg.address = page;
  142.     fr.address = frame;
  143.  
  144.     tag.value = ASID_KERNEL;
  145.     tag.vpn = pg.vpn;
  146.  
  147.     dtlb_tag_access_write(tag.value);
  148.  
  149.     data.value = 0;
  150.     data.v = true;
  151.     data.size = pagesize;
  152.     data.pfn = fr.pfn;
  153.     data.l = locked;
  154.     data.cp = cacheable;
  155.     data.cv = cacheable;
  156.     data.p = true;
  157.     data.w = true;
  158.     data.g = true;
  159.  
  160.     dtlb_data_in_write(data.value);
  161. }
  162.  
  163. /** ITLB miss handler. */
  164. void fast_instruction_access_mmu_miss(void)
  165. {
  166.     panic("%s\n", __FUNCTION__);
  167. }
  168.  
  169. /** DTLB miss handler. */
  170. void fast_data_access_mmu_miss(void)
  171. {
  172.     tlb_tag_access_reg_t tag;
  173.     uintptr_t tpc;
  174.     char *tpc_str;
  175.  
  176.     tag.value = dtlb_tag_access_read();
  177.     if (tag.context != ASID_KERNEL || tag.vpn == 0) {
  178.         tpc = tpc_read();
  179.         tpc_str = get_symtab_entry(tpc);
  180.  
  181.         printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
  182.         printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
  183.         panic("%s\n", __FUNCTION__);
  184.     }
  185.  
  186.     /*
  187.      * Identity map piece of faulting kernel address space.
  188.      */
  189.     dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
  190. }
  191.  
  192. /** DTLB protection fault handler. */
  193. void fast_data_access_protection(void)
  194. {
  195.     panic("%s\n", __FUNCTION__);
  196. }
  197.  
  198. /** Print contents of both TLBs. */
  199. void tlb_print(void)
  200. {
  201.     int i;
  202.     tlb_data_t d;
  203.     tlb_tag_read_reg_t t;
  204.    
  205.     printf("I-TLB contents:\n");
  206.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  207.         d.value = itlb_data_access_read(i);
  208.         t.value = itlb_tag_read_read(i);
  209.        
  210.         printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  211.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  212.     }
  213.  
  214.     printf("D-TLB contents:\n");
  215.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  216.         d.value = dtlb_data_access_read(i);
  217.         t.value = dtlb_tag_read_read(i);
  218.        
  219.         printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  220.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  221.     }
  222.  
  223. }
  224.  
  225. /** Invalidate all unlocked ITLB and DTLB entries. */
  226. void tlb_invalidate_all(void)
  227. {
  228.     int i;
  229.     tlb_data_t d;
  230.     tlb_tag_read_reg_t t;
  231.  
  232.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  233.         d.value = itlb_data_access_read(i);
  234.         if (!d.l) {
  235.             t.value = itlb_tag_read_read(i);
  236.             d.v = false;
  237.             itlb_tag_access_write(t.value);
  238.             itlb_data_access_write(i, d.value);
  239.         }
  240.     }
  241.    
  242.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  243.         d.value = dtlb_data_access_read(i);
  244.         if (!d.l) {
  245.             t.value = dtlb_tag_read_read(i);
  246.             d.v = false;
  247.             dtlb_tag_access_write(t.value);
  248.             dtlb_data_access_write(i, d.value);
  249.         }
  250.     }
  251.    
  252. }
  253.  
  254. /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
  255.  *
  256.  * @param asid Address Space ID.
  257.  */
  258. void tlb_invalidate_asid(asid_t asid)
  259. {
  260.     /* TODO: write asid to some Context register and encode the register in second parameter below. */
  261.     itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  262.     dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  263. }
  264.  
  265. /** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
  266.  *
  267.  * @param asid Address Space ID.
  268.  * @param page First page which to sweep out from ITLB and DTLB.
  269.  * @param cnt Number of ITLB and DTLB entries to invalidate.
  270.  */
  271. void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
  272. {
  273.     int i;
  274.    
  275.     for (i = 0; i < cnt; i++) {
  276.         /* TODO: write asid to some Context register and encode the register in second parameter below. */
  277.         itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
  278.         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
  279.     }
  280. }
  281.  
  282.  /** @}
  283.  */
  284.  
  285.