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  1. /*
  2.  * Copyright (C) 2003-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29.  /** @addtogroup mips32interrupt mips32
  30.  * @ingroup interrupt
  31.  * @{
  32.  */
  33. /** @file
  34.  */
  35.  
  36. #include <interrupt.h>
  37. #include <arch/interrupt.h>
  38. #include <arch/types.h>
  39. #include <arch.h>
  40. #include <arch/cp0.h>
  41. #include <time/clock.h>
  42. #include <arch/drivers/arc.h>
  43.  
  44. #include <ipc/sysipc.h>
  45.  
  46. /** Disable interrupts.
  47.  *
  48.  * @return Old interrupt priority level.
  49.  */
  50. ipl_t interrupts_disable(void)
  51. {
  52.     ipl_t ipl = (ipl_t) cp0_status_read();
  53.     cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
  54.     return ipl;
  55. }
  56.  
  57. /** Enable interrupts.
  58.  *
  59.  * @return Old interrupt priority level.
  60.  */
  61. ipl_t interrupts_enable(void)
  62. {
  63.     ipl_t ipl = (ipl_t) cp0_status_read();
  64.     cp0_status_write(ipl | cp0_status_ie_enabled_bit);
  65.     return ipl;
  66. }
  67.  
  68. /** Restore interrupt priority level.
  69.  *
  70.  * @param ipl Saved interrupt priority level.
  71.  */
  72. void interrupts_restore(ipl_t ipl)
  73. {
  74.     cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
  75. }
  76.  
  77. /** Read interrupt priority level.
  78.  *
  79.  * @return Current interrupt priority level.
  80.  */
  81. ipl_t interrupts_read(void)
  82. {
  83.     return cp0_status_read();
  84. }
  85.  
  86. /* TODO: This is SMP unsafe!!! */
  87. static unsigned long nextcount;
  88. /** Start hardware clock */
  89. static void timer_start(void)
  90. {
  91.     nextcount = cp0_compare_value + cp0_count_read();
  92.     cp0_compare_write(nextcount);
  93. }
  94.  
  95. static void timer_exception(int n, istate_t *istate)
  96. {
  97.     unsigned long drift;
  98.  
  99.     drift = cp0_count_read() - nextcount;
  100.     while (drift > cp0_compare_value) {
  101.         drift -= cp0_compare_value;
  102.         CPU->missed_clock_ticks++;
  103.     }
  104.     nextcount = cp0_count_read() + cp0_compare_value - drift;
  105.     cp0_compare_write(nextcount);
  106.     clock();
  107. }
  108.  
  109. static void swint0(int n, istate_t *istate)
  110. {
  111.     cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
  112.     ipc_irq_send_notif(0);
  113. }
  114.  
  115. static void swint1(int n, istate_t *istate)
  116. {
  117.     cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
  118.     ipc_irq_send_notif(1);
  119. }
  120.  
  121. /* Initialize basic tables for exception dispatching */
  122. void interrupt_init(void)
  123. {
  124.     int_register(TIMER_IRQ, "timer", timer_exception);
  125.     int_register(0, "swint0", swint0);
  126.     int_register(1, "swint1", swint1);
  127.     timer_start();
  128. }
  129.  
  130. static void ipc_int(int n, istate_t *istate)
  131. {
  132.     ipc_irq_send_notif(n-INT_OFFSET);
  133. }
  134.  
  135. /* Reregister irq to be IPC-ready */
  136. void irq_ipc_bind_arch(__native irq)
  137. {
  138.     /* Do not allow to redefine timer */
  139.     /* Swint0, Swint1 are already handled */
  140.     if (irq == TIMER_IRQ || irq < 2)
  141.         return;
  142.     int_register(irq, "ipc_int", ipc_int);
  143. }
  144.  
  145.  /** @}
  146.  */
  147.  
  148.