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  1. /*
  2.  * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29.  
  30. /** @addtogroup arm32boot
  31.  * @{
  32.  */
  33. /** @file
  34.  *  @brief Memory management used while booting the kernel.
  35.  *
  36.  *  So called "section" paging is used while booting the kernel. The term "section"
  37.  *  comes from the ARM architecture specification and stands for the following:
  38.  *  one-level paging, 1MB sized pages, 4096 entries in the page table.
  39.  */
  40.  
  41.  
  42. #ifndef BOOT_arm32__MM_H
  43. #define BOOT_arm32__MM_H
  44.  
  45.  
  46. #ifndef __ASM__
  47. #include "types.h"
  48. #endif
  49.  
  50.  
  51. /** Frame width. */
  52. #define FRAME_WIDTH                 20
  53.  
  54. /** Frame size. */
  55. #define FRAME_SIZE                  (1 << FRAME_WIDTH)
  56.  
  57. /** Page size in 2-level paging which is switched on later after the kernel initialization. */
  58. #define KERNEL_PAGE_SIZE            (1 << 12)
  59.  
  60.  
  61. #ifndef __ASM__
  62. /** Converts kernel address to physical address. */
  63. #   define KA2PA(x)                 (((uintptr_t) (x)) - 0x80000000)
  64. /** Converts physical address to kernel address. */
  65. #   define PA2KA(x)                 (((uintptr_t) (x)) + 0x80000000)
  66. #else
  67. #   define KA2PA(x)                 ((x) - 0x80000000)
  68. #   define PA2KA(x)                 ((x) + 0x80000000)
  69. #endif
  70.  
  71.  
  72. /** Number of entries in PTL0. */
  73. #define PTL0_ENTRIES                (1<<12)             /* 4096 */
  74.  
  75. /** Size of an entry in PTL0. */
  76. #define PTL0_ENTRY_SIZE             4
  77.  
  78. /** Returns number of frame the address belongs to. */
  79. #define ADDR2PFN( addr )            ( ((uintptr_t)(addr)) >> FRAME_WIDTH )
  80.  
  81. /** Describes "section" page table entry (one-level paging with 1MB sized pages). */  
  82. #define PTE_DESCRIPTOR_SECTION      0x2
  83.  
  84. /** Page table access rights: user - no access, kernel - read/write. */
  85. #define PTE_AP_USER_NO_KERNEL_RW    0x1
  86.  
  87.  
  88. #ifndef __ASM__
  89.  
  90.  
  91. /** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized
  92.  * pages). Used only while booting the kernel.
  93.  */
  94. typedef struct {
  95.     unsigned descriptor_type     : 2;
  96.     unsigned bufferable          : 1;
  97.     unsigned cacheable           : 1;
  98.     unsigned impl_specific       : 1;
  99.     unsigned domain              : 4;
  100.     unsigned should_be_zero_1    : 1;
  101.     unsigned access_permission   : 2;  
  102.     unsigned should_be_zero_2    : 8;
  103.     unsigned section_base_addr   : 12;
  104. } __attribute__ ((packed)) pte_level0_section_t;
  105.  
  106.  
  107. /** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */
  108. extern pte_level0_section_t page_table[PTL0_ENTRIES];
  109.  
  110. extern void mmu_start(void);
  111.  
  112.  
  113. /** Enables paging. */
  114. static inline void enable_paging()
  115. {
  116.     /* c3 - each two bits controls access to the one of domains (16)
  117.      *      0b01 - behave as a client (user) of a domain
  118.      */
  119.     asm volatile (
  120.         // behave as a client of domains
  121.         "ldr r0, =0x55555555       \n"
  122.         "mcr p15, 0, r0, c3, c0, 0 \n"
  123.  
  124.         // current settings
  125.         "mrc p15, 0, r0, c1, c0, 0 \n"
  126.  
  127.         // mask to enable paging
  128.         "ldr r1, =0x00000001       \n"
  129.         "orr r0, r0, r1            \n"
  130.  
  131.         // store settings
  132.         "mcr p15, 0, r0, c1, c0, 0 \n"
  133.         :
  134.         :
  135.         : "r0", "r1"
  136.     );
  137. }
  138.  
  139.  
  140. /** Sets the address of level 0 page table to CP15 register 2.
  141.  *
  142.  * @param pt Address of a page table to set.
  143.  */  
  144. static inline void set_ptl0_address(pte_level0_section_t* pt)
  145. {
  146.     asm volatile (
  147.         "mcr p15, 0, %0, c2, c0, 0 \n"
  148.         :
  149.         : "r"(pt)
  150.     );
  151. }
  152.  
  153.  
  154. #endif
  155.  
  156. #endif
  157.  
  158. /** @}
  159.  */
  160.  
  161.