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  1. /*
  2.  * Copyright (c) 2006 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64mm  
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/mm/tsb.h>
  36. #include <arch/mm/tlb.h>
  37. #include <arch/mm/page.h>
  38. #include <arch/barrier.h>
  39. #include <mm/as.h>
  40. #include <arch/types.h>
  41. #include <macros.h>
  42. #include <debug.h>
  43.  
  44. #define TSB_INDEX_MASK  ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
  45.  
  46. /** Invalidate portion of TSB.
  47.  *
  48.  * We assume that the address space is already locked. Note that respective
  49.  * portions of both TSBs are invalidated at a time.
  50.  *
  51.  * @param as Address space.
  52.  * @param page First page to invalidate in TSB.
  53.  * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
  54.  *  whole TSB.
  55.  */
  56. void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
  57. {
  58.     index_t i0, i;
  59.     count_t cnt;
  60.    
  61.     ASSERT(as->arch.itsb && as->arch.dtsb);
  62.    
  63.     i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
  64.     if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
  65.         cnt = ITSB_ENTRY_COUNT;
  66.     else
  67.         cnt = pages * 2;
  68.    
  69.     for (i = 0; i < cnt; i++) {
  70.         as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
  71.             true;
  72.         as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
  73.             true;
  74.     }
  75. }
  76.  
  77. /** Copy software PTE to ITSB.
  78.  *
  79.  * @param t     Software PTE.
  80.  * @param index Zero if lower 8K-subpage, one if higher 8K subpage.
  81.  */
  82. void itsb_pte_copy(pte_t *t, index_t index)
  83. {
  84.     as_t *as;
  85.     tsb_entry_t *tsb;
  86.     index_t entry;
  87.    
  88.     as = t->as;
  89.     entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
  90.     tsb = &as->arch.itsb[entry];
  91.  
  92.     /*
  93.      * We use write barriers to make sure that the TSB load
  94.      * won't use inconsistent data or that the fault will
  95.      * be repeated.
  96.      */
  97.  
  98.     tsb->tag.invalid = true;    /* invalidate the entry
  99.                      * (tag target has this
  100.                      * set to 0) */
  101.  
  102.     write_barrier();
  103.  
  104.     tsb->tag.context = as->asid;
  105.     tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
  106.         VA_TAG_PAGE_SHIFT;
  107.     tsb->data.value = 0;
  108.     tsb->data.size = PAGESIZE_8K;
  109.     tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
  110.     tsb->data.cp = t->c;
  111.     tsb->data.p = t->k;     /* p as privileged */
  112.     tsb->data.v = t->p;
  113.    
  114.     write_barrier();
  115.    
  116.     tsb->tag.invalid = false;   /* mark the entry as valid */
  117. }
  118.  
  119. /** Copy software PTE to DTSB.
  120.  *
  121.  * @param t Software PTE.
  122.  * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
  123.  * @param ro    If true, the mapping is copied read-only.
  124.  */
  125. void dtsb_pte_copy(pte_t *t, index_t index, bool ro)
  126. {
  127.     as_t *as;
  128.     tsb_entry_t *tsb;
  129.     index_t entry;
  130.    
  131.     as = t->as;
  132.     entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
  133.     tsb = &as->arch.dtsb[entry];
  134.  
  135.     /*
  136.      * We use write barriers to make sure that the TSB load
  137.      * won't use inconsistent data or that the fault will
  138.      * be repeated.
  139.      */
  140.  
  141.     tsb->tag.invalid = true;    /* invalidate the entry
  142.                      * (tag target has this
  143.                      * set to 0) */
  144.  
  145.     write_barrier();
  146.  
  147.     tsb->tag.context = as->asid;
  148.     tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
  149.         VA_TAG_PAGE_SHIFT;
  150.     tsb->data.value = 0;
  151.     tsb->data.size = PAGESIZE_8K;
  152.     tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
  153.     tsb->data.cp = t->c;
  154. #ifdef CONFIG_VIRT_IDX_DCACHE
  155.     tsb->data.cv = t->c;
  156. #endif /* CONFIG_VIRT_IDX_DCACHE */
  157.     tsb->data.p = t->k;     /* p as privileged */
  158.     tsb->data.w = ro ? false : t->w;
  159.     tsb->data.v = t->p;
  160.    
  161.     write_barrier();
  162.    
  163.     tsb->tag.invalid = false;   /* mark the entry as valid */
  164. }
  165.  
  166. /** @}
  167.  */
  168.