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  1. /*
  2.  * Copyright (c) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_sparc64_BARRIER_H_
  36. #define KERN_sparc64_BARRIER_H_
  37.  
  38. /*
  39.  * Our critical section barriers are prepared for the weakest RMO memory model.
  40.  */
  41. #define CS_ENTER_BARRIER()              \
  42.     asm volatile (                  \
  43.         "membar #LoadLoad | #LoadStore\n"   \
  44.         ::: "memory"                \
  45.     )
  46. #define CS_LEAVE_BARRIER()              \
  47.     asm volatile (                  \
  48.         "membar #StoreStore\n"          \
  49.         "membar #LoadStore\n"           \
  50.         ::: "memory"                \
  51.     )
  52.  
  53. #define memory_barrier()    \
  54.     asm volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
  55. #define read_barrier()      \
  56.     asm volatile ("membar #LoadLoad\n" ::: "memory")
  57. #define write_barrier()     \
  58.     asm volatile ("membar #StoreStore\n" ::: "memory")
  59.  
  60. /** Flush Instruction Memory instruction. */
  61. static inline void flush(void)
  62. {
  63.     /*
  64.      * The FLUSH instruction takes address parameter.
  65.      * As such, it may trap if the address is not found in DTLB.
  66.      *
  67.      * The entire kernel text is mapped by a locked ITLB and
  68.      * DTLB entries. Therefore, when this function is called,
  69.      * the %o7 register will always be in the range mapped by
  70.      * DTLB.
  71.      */
  72.      
  73.         asm volatile ("flush %o7\n");
  74. }
  75.  
  76. /** Memory Barrier instruction. */
  77. static inline void membar(void)
  78. {
  79.     asm volatile ("membar #Sync\n");
  80. }
  81.  
  82. #endif
  83.  
  84. /** @}
  85.  */
  86.