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Rev 3925 Rev 3926
Line 77... Line 77...
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		port/i8042.c \
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		port/i8042.c \
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		ctl/pc.c
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		ctl/pc.c
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endif
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endif
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ifeq ($(UARCH), ia64)
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ifeq ($(UARCH), ia64)
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	GENARCH_SOURCES += \
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	GENARCH_SOURCES += \
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		port/dummy.c \
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		port/i8042.c \
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		ctl/stty.c
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		ctl/pc.c
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endif
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endif
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ifeq ($(MACHINE), msim)
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ifeq ($(MACHINE), msim)
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	GENARCH_SOURCES += \
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	GENARCH_SOURCES += \
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		port/msim.c \
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		port/msim.c \
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		ctl/stty.c
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		ctl/stty.c