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34 | * @brief EBUS 'reg' and 'ranges' properties handling. |
34 | * @brief EBUS 'reg' and 'ranges' properties handling. |
35 | * |
35 | * |
36 | */ |
36 | */ |
37 | 37 | ||
38 | #include <genarch/ofw/ofw_tree.h> |
38 | #include <genarch/ofw/ofw_tree.h> |
- | 39 | #include <arch/drivers/pci.h> |
|
39 | #include <arch/memstr.h> |
40 | #include <arch/memstr.h> |
- | 41 | #include <arch/trap/interrupt.h> |
|
40 | #include <func.h> |
42 | #include <func.h> |
41 | #include <panic.h> |
43 | #include <panic.h> |
42 | #include <debug.h> |
44 | #include <debug.h> |
43 | #include <macros.h> |
45 | #include <macros.h> |
44 | 46 | ||
- | 47 | /** Apply EBUS ranges to EBUS register. */ |
|
45 | bool ofw_ebus_apply_ranges(ofw_tree_node_t *node, ofw_ebus_reg_t *reg, uintptr_t *pa) |
48 | bool ofw_ebus_apply_ranges(ofw_tree_node_t *node, ofw_ebus_reg_t *reg, uintptr_t *pa) |
46 | { |
49 | { |
47 | ofw_tree_property_t *prop; |
50 | ofw_tree_property_t *prop; |
48 | ofw_ebus_range_t *range; |
51 | ofw_ebus_range_t *range; |
49 | count_t ranges; |
52 | count_t ranges; |
Line 110... | Line 113... | ||
110 | 113 | ||
111 | found: |
114 | found: |
112 | /* |
115 | /* |
113 | * We found the device that functions as an interrupt controller |
116 | * We found the device that functions as an interrupt controller |
114 | * for the interrupt. We also found mapping from interrupt to INR. |
117 | * for the interrupt. We also found mapping from interrupt to INR. |
- | 118 | * What needs to be done now is to verify that this indeed is a PCI |
|
- | 119 | * node. |
|
115 | */ |
120 | */ |
116 | 121 | ||
117 | controller = ofw_tree_find_node_by_handle(ofw_tree_lookup("/"), intr_map[i].controller_handle); |
122 | controller = ofw_tree_find_node_by_handle(ofw_tree_lookup("/"), intr_map[i].controller_handle); |
- | 123 | if (!controller) |
|
- | 124 | return false; |
|
118 | 125 | ||
- | 126 | if (strcmp(ofw_tree_node_name(controller), "pci") != 0) { |
|
- | 127 | /* |
|
- | 128 | * This is not a PCI node. |
|
- | 129 | */ |
|
- | 130 | return false; |
|
- | 131 | } |
|
- | 132 | ||
- | 133 | pci_t *pci = controller->device; |
|
- | 134 | if (!pci) { |
|
- | 135 | pci = pci_init(controller); |
|
- | 136 | if (!pci) |
|
- | 137 | return false; |
|
- | 138 | controller->device = pci; |
|
- | 139 | ||
- | 140 | } |
|
- | 141 | pci_enable_interrupt(pci, intr_map[i].controller_inr); |
|
- | 142 | ||
119 | *inr = intr_map[i].controller_inr; |
143 | *inr = intr_map[i].controller_inr; |
- | 144 | *inr |= 0x1f << IGN_SHIFT; /* 0x1f is hardwired IGN */ |
|
- | 145 | ||
120 | return true; |
146 | return true; |
121 | } |
147 | } |
122 | 148 | ||
123 | /** @} |
149 | /** @} |
124 | */ |
150 | */ |