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| 39 | #include <arch/asm.h> |
39 | #include <arch/asm.h> |
| 40 | #include <mm/slab.h> |
40 | #include <mm/slab.h> |
| 41 | #include <ddi/device.h> |
41 | #include <ddi/device.h> |
| 42 | #include <synch/spinlock.h> |
42 | #include <synch/spinlock.h> |
| 43 | 43 | ||
| 44 | static void cuda_packet_handle(cuda_instance_t *instance, size_t len); |
44 | static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *buf, size_t len); |
| - | 45 | static void cuda_irq_listen(irq_t *irq); |
|
| - | 46 | static void cuda_irq_receive(irq_t *irq); |
|
| - | 47 | static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len); |
|
| 45 | 48 | ||
| 46 | /** B register fields */ |
49 | /** B register fields */ |
| 47 | enum { |
50 | enum { |
| 48 | TREQ = 0x08, |
51 | TREQ = 0x08, |
| 49 | TACK = 0x10, |
52 | TACK = 0x10, |
| 50 | TIP = 0x20 |
53 | TIP = 0x20 |
| 51 | }; |
54 | }; |
| 52 | 55 | ||
| 53 | /** IER register fields */ |
56 | /** IER register fields */ |
| 54 | enum { |
57 | enum { |
| - | 58 | IER_CLR = 0x00, |
|
| 55 | IER_SET = 0x80, |
59 | IER_SET = 0x80, |
| - | 60 | ||
| 56 | SR_INT = 0x04 |
61 | SR_INT = 0x04, |
| - | 62 | ALL_INT = 0x7f |
|
| - | 63 | }; |
|
| - | 64 | ||
| - | 65 | /** ACR register fields */ |
|
| - | 66 | enum { |
|
| - | 67 | SR_OUT = 0x10 |
|
| 57 | }; |
68 | }; |
| 58 | 69 | ||
| - | 70 | #include <print.h> |
|
| 59 | static irq_ownership_t cuda_claim(irq_t *irq) |
71 | static irq_ownership_t cuda_claim(irq_t *irq) |
| 60 | { |
72 | { |
| 61 | cuda_instance_t *instance = irq->instance; |
73 | cuda_instance_t *instance = irq->instance; |
| 62 | cuda_t *dev = instance->cuda; |
74 | cuda_t *dev = instance->cuda; |
| 63 | uint8_t ifr; |
75 | uint8_t ifr; |
| 64 | 76 | ||
| 65 | ifr = pio_read_8(&dev->ifr); |
77 | ifr = pio_read_8(&dev->ifr); |
| 66 | 78 | ||
| 67 | if ((ifr & SR_INT) != 0) |
79 | if ((ifr & SR_INT) == 0) |
| 68 | return IRQ_ACCEPT; |
- | |
| 69 | else |
- | |
| 70 | return IRQ_DECLINE; |
80 | return IRQ_DECLINE; |
| - | 81 | ||
| - | 82 | return IRQ_ACCEPT; |
|
| 71 | } |
83 | } |
| 72 | 84 | ||
| 73 | static void cuda_irq_handler(irq_t *irq) |
85 | static void cuda_irq_handler(irq_t *irq) |
| 74 | { |
86 | { |
| 75 | cuda_instance_t *instance = irq->instance; |
87 | cuda_instance_t *instance = irq->instance; |
| 76 | cuda_t *dev = instance->cuda; |
88 | uint8_t rbuf[CUDA_RCV_BUF_SIZE]; |
| - | 89 | size_t len; |
|
| - | 90 | bool handle; |
|
| - | 91 | ||
| 77 | uint8_t b, data; |
92 | handle = false; |
| 78 | size_t pos; |
93 | len = 0; |
| 79 | 94 | ||
| 80 | spinlock_lock(&instance->dev_lock); |
95 | spinlock_lock(&instance->dev_lock); |
| 81 | 96 | ||
| 82 | /* We have received one or more CUDA packets. Process them all. */ |
97 | /* Lower IFR.SR_INT so that CUDA can generate next int by raising it. */ |
| 83 | while (true) { |
- | |
| 84 | b = pio_read_8(&dev->b); |
98 | pio_write_8(&instance->cuda->ifr, SR_INT); |
| 85 | 99 | ||
| 86 | if ((b & TREQ) != 0) |
100 | switch (instance->xstate) { |
| - | 101 | case cx_listen: cuda_irq_listen(irq); break; |
|
| - | 102 | case cx_receive: cuda_irq_receive(irq); break; |
|
| - | 103 | case cx_rcv_end: cuda_irq_rcv_end(irq, rbuf, &len); |
|
| 87 | break; /* No data */ |
104 | handle = true; break; |
| - | 105 | } |
|
| 88 | 106 | ||
| 89 | pio_write_8(&dev->b, b & ~TIP); |
107 | spinlock_unlock(&instance->dev_lock); |
| 90 | 108 | ||
| 91 | /* Read one packet. */ |
109 | /* Handle an incoming packet. */ |
| - | 110 | if (handle) |
|
| - | 111 | cuda_packet_handle(instance, rbuf, len); |
|
| - | 112 | } |
|
| 92 | 113 | ||
| 93 | pos = 0; |
114 | /** Interrupt in listen state. |
| 94 | do { |
115 | * |
| 95 | data = pio_read_8(&dev->sr); |
116 | * Start packet reception. |
| 96 | b = pio_read_8(&dev->b); |
117 | */ |
| 97 | pio_write_8(&dev->b, b ^ TACK); |
118 | static void cuda_irq_listen(irq_t *irq) |
| 98 | 119 | { |
|
| 99 | if (pos < CUDA_RCV_BUF_SIZE) |
120 | cuda_instance_t *instance = irq->instance; |
| 100 | instance->rcv_buf[pos++] = data; |
121 | cuda_t *dev = instance->cuda; |
| 101 | } while ((b & TREQ) == 0); |
122 | uint8_t b; |
| 102 | 123 | ||
| 103 | pio_write_8(&dev->b, b | TACK | TIP); |
124 | b = pio_read_8(&dev->b); |
| 104 | 125 | ||
| - | 126 | if ((b & TREQ) != 0) { |
|
| 105 | cuda_packet_handle(instance, pos); |
127 | printf("cuda_irq_listen: no TREQ?!\n"); |
| - | 128 | return; |
|
| 106 | } |
129 | } |
| 107 | 130 | ||
| - | 131 | pio_read_8(&dev->sr); |
|
| - | 132 | pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP); |
|
| 108 | spinlock_unlock(&instance->dev_lock); |
133 | instance->xstate = cx_receive; |
| 109 | } |
134 | } |
| 110 | 135 | ||
| - | 136 | /** Interrupt in receive state. |
|
| - | 137 | * |
|
| - | 138 | * Receive next byte of packet. |
|
| - | 139 | */ |
|
| 111 | static void cuda_packet_handle(cuda_instance_t *instance, size_t len) |
140 | static void cuda_irq_receive(irq_t *irq) |
| 112 | { |
141 | { |
| - | 142 | cuda_instance_t *instance = irq->instance; |
|
| 113 | uint8_t *data = instance->rcv_buf; |
143 | cuda_t *dev = instance->cuda; |
| - | 144 | uint8_t b, data; |
|
| - | 145 | ||
| - | 146 | data = pio_read_8(&dev->sr); |
|
| - | 147 | if (instance->bidx < CUDA_RCV_BUF_SIZE) |
|
| - | 148 | instance->rcv_buf[instance->bidx++] = data; |
|
| - | 149 | ||
| - | 150 | b = pio_read_8(&dev->b); |
|
| - | 151 | ||
| - | 152 | if ((b & TREQ) == 0) { |
|
| - | 153 | pio_write_8(&dev->b, b ^ TACK); |
|
| - | 154 | } else { |
|
| - | 155 | pio_write_8(&dev->b, b | TACK | TIP); |
|
| - | 156 | instance->xstate = cx_rcv_end; |
|
| - | 157 | } |
|
| - | 158 | } |
|
| - | 159 | ||
| - | 160 | /** Interrupt in rcv_end state. |
|
| - | 161 | * |
|
| - | 162 | * Terminate packet reception. Either go back to listen state or start |
|
| - | 163 | * receiving another packet if CUDA has one for us. |
|
| - | 164 | */ |
|
| - | 165 | static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len) |
|
| - | 166 | { |
|
| - | 167 | cuda_instance_t *instance = irq->instance; |
|
| - | 168 | cuda_t *dev = instance->cuda; |
|
| - | 169 | uint8_t data, b; |
|
| - | 170 | ||
| - | 171 | b = pio_read_8(&dev->b); |
|
| - | 172 | data = pio_read_8(&dev->sr); |
|
| 114 | 173 | ||
| - | 174 | instance->xstate = cx_listen; |
|
| - | 175 | ||
| - | 176 | if ((b & TREQ) == 0) { |
|
| - | 177 | instance->xstate = cx_receive; |
|
| - | 178 | pio_write_8(&dev->b, b & ~TIP); |
|
| - | 179 | } else { |
|
| - | 180 | instance->xstate = cx_listen; |
|
| - | 181 | } |
|
| - | 182 | ||
| - | 183 | memcpy(buf, instance->rcv_buf, instance->bidx); |
|
| - | 184 | *len = instance->bidx; |
|
| - | 185 | instance->bidx = 0; |
|
| - | 186 | } |
|
| - | 187 | ||
| - | 188 | static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *data, size_t len) |
|
| - | 189 | { |
|
| 115 | if (data[0] != 0x00 || data[1] != 0x40 || data[2] != 0x2c) |
190 | if (data[0] != 0x00 || data[1] != 0x40 || (data[2] != 0x2c |
| - | 191 | && data[2] != 0x8c)) |
|
| 116 | return; |
192 | return; |
| 117 | 193 | ||
| 118 | /* The packet contains one or two scancodes. */ |
194 | /* The packet contains one or two scancodes. */ |
| 119 | if (data[3] != 0xff) |
195 | if (data[3] != 0xff) |
| 120 | indev_push_character(instance->kbrdin, data[3]); |
196 | indev_push_character(instance->kbrdin, data[3]); |
| Line 127... | Line 203... | ||
| 127 | cuda_instance_t *instance |
203 | cuda_instance_t *instance |
| 128 | = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC); |
204 | = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC); |
| 129 | if (instance) { |
205 | if (instance) { |
| 130 | instance->cuda = dev; |
206 | instance->cuda = dev; |
| 131 | instance->kbrdin = NULL; |
207 | instance->kbrdin = NULL; |
| - | 208 | instance->xstate = cx_listen; |
|
| - | 209 | instance->bidx = 0; |
|
| 132 | 210 | ||
| 133 | spinlock_initialize(&instance->dev_lock, "cuda_dev"); |
211 | spinlock_initialize(&instance->dev_lock, "cuda_dev"); |
| 134 | 212 | ||
| - | 213 | /* Disable all interrupts from CUDA. */ |
|
| - | 214 | pio_write_8(&dev->ier, IER_CLR | ALL_INT); |
|
| - | 215 | ||
| 135 | irq_initialize(&instance->irq); |
216 | irq_initialize(&instance->irq); |
| 136 | instance->irq.devno = device_assign_devno(); |
217 | instance->irq.devno = device_assign_devno(); |
| 137 | instance->irq.inr = inr; |
218 | instance->irq.inr = inr; |
| 138 | instance->irq.claim = cuda_claim; |
219 | instance->irq.claim = cuda_claim; |
| 139 | instance->irq.handler = cuda_irq_handler; |
220 | instance->irq.handler = cuda_irq_handler; |
| 140 | instance->irq.instance = instance; |
221 | instance->irq.instance = instance; |
| 141 | instance->irq.cir = cir; |
222 | instance->irq.cir = cir; |
| 142 | instance->irq.cir_arg = cir_arg; |
223 | instance->irq.cir_arg = cir_arg; |
| - | 224 | instance->irq.preack = true; |
|
| 143 | } |
225 | } |
| 144 | 226 | ||
| 145 | return instance; |
227 | return instance; |
| 146 | } |
228 | } |
| 147 | 229 | ||
| 148 | void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin) |
230 | void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin) |
| 149 | { |
231 | { |
| - | 232 | cuda_t *dev = instance->cuda; |
|
| - | 233 | ||
| 150 | ASSERT(instance); |
234 | ASSERT(instance); |
| 151 | ASSERT(kbrdin); |
235 | ASSERT(kbrdin); |
| 152 | 236 | ||
| 153 | instance->kbrdin = kbrdin; |
237 | instance->kbrdin = kbrdin; |
| 154 | irq_register(&instance->irq); |
238 | irq_register(&instance->irq); |
| 155 | 239 | ||
| 156 | /* Enable SR interrupt. */ |
240 | /* Enable SR interrupt. */ |
| - | 241 | pio_write_8(&dev->ier, TIP | TREQ); |
|
| 157 | pio_write_8(&instance->cuda->ier, IER_SET | SR_INT); |
242 | pio_write_8(&dev->ier, IER_SET | SR_INT); |
| 158 | } |
243 | } |
| 159 | 244 | ||
| 160 | /** @} |
245 | /** @} |
| 161 | */ |
246 | */ |