Rev 4311 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 4311 | Rev 4610 | ||
|---|---|---|---|
| Line 1... | Line 1... | ||
| 1 | /* |
1 | /* |
| 2 | * Copyright (c) 2006 Martin Decky |
2 | * Copyright (c) 2006 Martin Decky |
| - | 3 | * Copyright (c) 2009 Jiri Svoboda |
|
| 3 | * All rights reserved. |
4 | * All rights reserved. |
| 4 | * |
5 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
8 | * are met: |
| Line 36... | Line 37... | ||
| 36 | #include <console/chardev.h> |
37 | #include <console/chardev.h> |
| 37 | #include <ddi/irq.h> |
38 | #include <ddi/irq.h> |
| 38 | #include <arch/asm.h> |
39 | #include <arch/asm.h> |
| 39 | #include <mm/slab.h> |
40 | #include <mm/slab.h> |
| 40 | #include <ddi/device.h> |
41 | #include <ddi/device.h> |
| - | 42 | #include <synch/spinlock.h> |
|
| - | 43 | ||
| - | 44 | static void cuda_packet_handle(cuda_instance_t *instance, size_t len); |
|
| - | 45 | ||
| - | 46 | /** B register fields */ |
|
| - | 47 | enum { |
|
| - | 48 | TREQ = 0x08, |
|
| - | 49 | TACK = 0x10, |
|
| - | 50 | TIP = 0x20 |
|
| - | 51 | }; |
|
| - | 52 | ||
| - | 53 | /** IER register fields */ |
|
| - | 54 | enum { |
|
| - | 55 | IER_SET = 0x80, |
|
| - | 56 | SR_INT = 0x04 |
|
| - | 57 | }; |
|
| 41 | 58 | ||
| 42 | static irq_ownership_t cuda_claim(irq_t *irq) |
59 | static irq_ownership_t cuda_claim(irq_t *irq) |
| 43 | { |
60 | { |
| - | 61 | cuda_instance_t *instance = irq->instance; |
|
| - | 62 | cuda_t *dev = instance->cuda; |
|
| - | 63 | uint8_t ifr; |
|
| - | 64 | ||
| - | 65 | ifr = pio_read_8(&dev->ifr); |
|
| - | 66 | ||
| - | 67 | if ((ifr & SR_INT) != 0) |
|
| - | 68 | return IRQ_ACCEPT; |
|
| - | 69 | else |
|
| 44 | return IRQ_DECLINE; |
70 | return IRQ_DECLINE; |
| 45 | } |
71 | } |
| 46 | 72 | ||
| 47 | static void cuda_irq_handler(irq_t *irq) |
73 | static void cuda_irq_handler(irq_t *irq) |
| 48 | { |
74 | { |
| - | 75 | cuda_instance_t *instance = irq->instance; |
|
| - | 76 | cuda_t *dev = instance->cuda; |
|
| - | 77 | uint8_t b, data; |
|
| - | 78 | size_t pos; |
|
| - | 79 | ||
| - | 80 | spinlock_lock(&instance->dev_lock); |
|
| - | 81 | ||
| - | 82 | /* We have received one or more CUDA packets. Process them all. */ |
|
| - | 83 | while (true) { |
|
| - | 84 | b = pio_read_8(&dev->b); |
|
| - | 85 | ||
| - | 86 | if ((b & TREQ) != 0) |
|
| - | 87 | break; /* No data */ |
|
| - | 88 | ||
| - | 89 | pio_write_8(&dev->b, b & ~TIP); |
|
| - | 90 | ||
| - | 91 | /* Read one packet. */ |
|
| - | 92 | ||
| - | 93 | pos = 0; |
|
| - | 94 | do { |
|
| - | 95 | data = pio_read_8(&dev->sr); |
|
| - | 96 | b = pio_read_8(&dev->b); |
|
| - | 97 | pio_write_8(&dev->b, b ^ TACK); |
|
| - | 98 | ||
| - | 99 | if (pos < CUDA_RCV_BUF_SIZE) |
|
| - | 100 | instance->rcv_buf[pos++] = data; |
|
| - | 101 | } while ((b & TREQ) == 0); |
|
| - | 102 | ||
| - | 103 | pio_write_8(&dev->b, b | TACK | TIP); |
|
| - | 104 | ||
| - | 105 | cuda_packet_handle(instance, pos); |
|
| - | 106 | } |
|
| - | 107 | ||
| - | 108 | spinlock_unlock(&instance->dev_lock); |
|
| - | 109 | } |
|
| - | 110 | ||
| - | 111 | static void cuda_packet_handle(cuda_instance_t *instance, size_t len) |
|
| - | 112 | { |
|
| - | 113 | uint8_t *data = instance->rcv_buf; |
|
| - | 114 | ||
| - | 115 | if (data[0] != 0x00 || data[1] != 0x40 || data[2] != 0x2c) |
|
| - | 116 | return; |
|
| - | 117 | ||
| - | 118 | /* The packet contains one or two scancodes. */ |
|
| - | 119 | if (data[3] != 0xff) |
|
| - | 120 | indev_push_character(instance->kbrdin, data[3]); |
|
| - | 121 | if (data[4] != 0xff) |
|
| - | 122 | indev_push_character(instance->kbrdin, data[4]); |
|
| 49 | } |
123 | } |
| 50 | 124 | ||
| 51 | cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg) |
125 | cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg) |
| 52 | { |
126 | { |
| 53 | cuda_instance_t *instance |
127 | cuda_instance_t *instance |
| 54 | = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC); |
128 | = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC); |
| 55 | if (instance) { |
129 | if (instance) { |
| 56 | instance->cuda = dev; |
130 | instance->cuda = dev; |
| 57 | instance->kbrdin = NULL; |
131 | instance->kbrdin = NULL; |
| - | 132 | ||
| - | 133 | spinlock_initialize(&instance->dev_lock, "cuda_dev"); |
|
| 58 | 134 | ||
| 59 | irq_initialize(&instance->irq); |
135 | irq_initialize(&instance->irq); |
| 60 | instance->irq.devno = device_assign_devno(); |
136 | instance->irq.devno = device_assign_devno(); |
| 61 | instance->irq.inr = inr; |
137 | instance->irq.inr = inr; |
| 62 | instance->irq.claim = cuda_claim; |
138 | instance->irq.claim = cuda_claim; |
| 63 | instance->irq.handler = cuda_irq_handler; |
139 | instance->irq.handler = cuda_irq_handler; |
| Line 69... | Line 145... | ||
| 69 | return instance; |
145 | return instance; |
| 70 | } |
146 | } |
| 71 | 147 | ||
| 72 | void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin) |
148 | void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin) |
| 73 | { |
149 | { |
| - | 150 | ASSERT(instance); |
|
| 74 | } |
151 | ASSERT(kbrdin); |
| 75 | 152 | ||
| - | 153 | instance->kbrdin = kbrdin; |
|
| - | 154 | irq_register(&instance->irq); |
|
| - | 155 | ||
| - | 156 | /* Enable SR interrupt. */ |
|
| - | 157 | pio_write_8(&instance->cuda->ier, IER_SET | SR_INT); |
|
| - | 158 | } |
|
| 76 | 159 | ||
| 77 | /** @} |
160 | /** @} |
| 78 | */ |
161 | */ |