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#include <arch/types.h>
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#include <arch/types.h>
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#include <debug.h>
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#include <debug.h>
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#include <ipc/sysipc.h>
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#include <ipc/sysipc.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <arch/barrier.h>
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#include <arch/barrier.h>
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#include <print.h>
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#include <genarch/kbd/z8530.h>
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#include <genarch/kbd/z8530.h>
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/** Register Interrupt Level Handler.
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/** Register Interrupt Level Handler.
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 *
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 *
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 * @param n Interrupt Level (1 - 15).
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 * @param n Interrupt Level (1 - 15).
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}
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}
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/* Reregister irq to be IPC-ready */
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/* Reregister irq to be IPC-ready */
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void irq_ipc_bind_arch(unative_t irq)
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void irq_ipc_bind_arch(unative_t irq)
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{
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{
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    /* TODO */
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#ifdef CONFIG_Z8530
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    z8530_belongs_to_kernel = false;
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#endif
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}
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}
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void interrupt(int n, istate_t *istate)
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void interrupt(int n, istate_t *istate)
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{
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{
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    uint64_t intrcv;
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    uint64_t intrcv;
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         * Since we don't have enough information about the FHC and
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         * Since we don't have enough information about the FHC and
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         * because the interrupt looks like level sensitive,
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         * because the interrupt looks like level sensitive,
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         * we cannot handle it by scheduling one of the level
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         * we cannot handle it by scheduling one of the level
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         * interrupt traps. Call the interrupt handler directly.
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         * interrupt traps. Call the interrupt handler directly.
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         */
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         */
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        if (z8530_belongs_to_kernel)
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            z8530_interrupt();
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        else
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            ipc_irq_send_notif(0);
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        fhc_uart_reset();
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        fhc_uart_reset();
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        z8530_interrupt();
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        break;
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        break;
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#endif
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#endif
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    }
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    }
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    membar();
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    membar();
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    asi_u64_write(ASI_INTR_RECEIVE, 0, 0);
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    asi_u64_write(ASI_INTR_RECEIVE, 0, 0);