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Line 120... Line 120...
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	! write DTLB tag
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	! write DTLB tag
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	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
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	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
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	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
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	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
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	membar #Sync
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	membar #Sync
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#ifdef CONFIG_VIRT_IDX_CACHE
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#define TTE_LOW_DATA(imm) 	(TTE_CP | TTE_CV | TTE_P | LMA | (imm))
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#else /* CONFIG_VIRT_IDX_CACHE */
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#define TTE_LOW_DATA(imm) 	(TTE_CP | TTE_P | LMA | (imm))
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#endif /* CONFIG_VIRT_IDX_CACHE */
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#define SET_TLB_DATA(r1, r2, imm) \
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#define SET_TLB_DATA(r1, r2, imm) \
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	set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \
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	set TTE_LOW_DATA(imm), %r1; \
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	or %r1, %l5, %r1; \
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	or %r1, %l5, %r1; \
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	mov PAGESIZE_4M, %r2; \
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	mov PAGESIZE_4M, %r2; \
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	sllx %r2, TTE_SIZE_SHIFT, %r2; \
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	sllx %r2, TTE_SIZE_SHIFT, %r2; \
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	or %r1, %r2, %r1; \
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	or %r1, %r2, %r1; \
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	mov 1, %r2; \
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	mov 1, %r2; \
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 * In runtime, it is further modified to reflect the starting address of
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 * In runtime, it is further modified to reflect the starting address of
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 * physical memory.
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 * physical memory.
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 */
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 */
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.global kernel_8k_tlb_data_template
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.global kernel_8k_tlb_data_template
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kernel_8k_tlb_data_template:
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kernel_8k_tlb_data_template:
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#ifdef CONFIG_VIRT_IDX_CACHE
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	.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_CV | TTE_P | TTE_W)
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#else /* CONFIG_VIRT_IDX_CACHE */
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	.quad ((1 << TTE_V_SHIFT) | TTE_CV | TTE_CP | TTE_P | TTE_W)
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	.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_P | TTE_W)
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#endif /* CONFIG_VIRT_IDX_CACHE */