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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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#include <arch/regdef.h>
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#include <arch/regdef.h>
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#include <arch/boot/boot.h>
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#include <arch/mm/mmu.h>
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#include <arch/mm/tlb.h>
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#include <arch/mm/tte.h>
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.register %g2, #scratch
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.register %g2, #scratch
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.register %g3, #scratch
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.register %g3, #scratch
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.register %g6, #scratch
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.register %g6, #scratch
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.register %g7, #scratch
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.register %g7, #scratch
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 * - identity mapping for memory stack
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 * - identity mapping for memory stack
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 */
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 */
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.global kernel_image_start
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.global kernel_image_start
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kernel_image_start:
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kernel_image_start:
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	flushw				! flush all but the active register window
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 60 
 
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	/*
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	/*
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	 * Disable interrupts and disable 32-bit address masking.
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	 * Setup basic runtime environment.
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	 */
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	 */
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	flushw				! flush all but the active register window
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	wrpr %g0, 0, %tl		! TL = 0, primary context register is used
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	! Disable interrupts and disable 32-bit address masking.
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	rdpr %pstate, %l0
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	rdpr %pstate, %g1
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	and %l0, ~(PSTATE_AM_BIT|PSTATE_IE_BIT), %l0
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	and %g1, ~(PSTATE_AM_BIT|PSTATE_IE_BIT), %g1
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	wrpr %l0, 0, %pstate
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	wrpr %g1, 0, %pstate
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	wrpr %r0, 0, %pil		! intialize %pil
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	/*
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	/*
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	 * Copy the bootinfo structure passed from the boot loader
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	 * Copy the bootinfo structure passed from the boot loader
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	 * to the kernel bootinfo structure.
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	 * to the kernel bootinfo structure.
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	 */
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	 */
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	mov %o0, %o1
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	mov %o0, %o1
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	set bootinfo, %o0
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	set bootinfo, %o0
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	call memcpy
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	call memcpy
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	nop
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	nop
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	set kernel_image_start, %o0
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	/*
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	/*
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	 * Take over control of MMU.
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	 * Switch to kernel trap table.
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	 */
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	set trap_table, %g1
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	wrpr %g1, 0, %tba
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	/*
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	 * Take over the DMMU by installing global locked
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	 * TTE entry identically mapping the first 4M
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	 * of memory.
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	 *
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	 *
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	 * First, take over DMMU for which we don't need to issue
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	 * In case of DMMU, no FLUSH instructions need to be
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	 * any FLUSH instructions. Because of that, we can
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	 * issued. Because of that, the old DTLB contents can
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	 * demap the old DTLB pretty straightforwardly.
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	 * be demapped pretty straightforwardly and without
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	 * causing any traps.
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	 */
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	 */
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	call take_over_tlb_and_tt
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	nop
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	wrpr %r0, 0, %pil
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	wr %g0, ASI_DMMU, %asi
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#define SET_TLB_DEMAP_CMD(r1, context_id) \
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	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
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	! demap context 0
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	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
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	stxa %g0, [%g1] ASI_DMMU_DEMAP
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	membar #Sync
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#define SET_TLB_TAG(r1, context) \
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	set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
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	! write DTLB tag
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	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
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	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
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	membar #Sync
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#define SET_TLB_DATA(r1, r2, imm) \
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	set TTE_L | TTE_CP | TTE_P | TTE_W | LMA | imm, %r1; \
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	set PAGESIZE_4M, %r2; \
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	sllx %r2, TTE_SIZE_SHIFT, %r2; \
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	or %r1, %r2, %r1; \
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	set 1, %r2; \
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	sllx %r2, TTE_V_SHIFT, %r2; \
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	or %r1, %r2, %r1;
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	! write DTLB data and install the kernel mapping
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	SET_TLB_DATA(g1, g2, TTE_G)
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	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
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	membar #Sync
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	/*
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	 * Now is time to take over the IMMU.
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	 * Unfortunatelly, it cannot be done as easily as the DMMU,
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	 * because the IMMU is mapping the code it executes.
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	 *
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	 * [ Note that brave experiments with disabling the IMMU
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	 * and using the DMMU approach failed after a dozen
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	 * of desparate days with only little success. ]
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	 *
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	 * The approach used here is inspired from OpenBSD.
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	 * First, the kernel creates IMMU mapping for itself
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	 * in context 1 (MEM_CONTEXT_TEMP) and switches to
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	 * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
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	 * afterwards and replaced with the kernel permanent
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	 * mapping. Finally, the kernel switches back to
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	 * context 0 and demaps context 1.
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	 *
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	 * Moreover, the IMMU requires use of the FLUSH instructions.
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	 * But that is OK because we always use operands with
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 153 
	 * addresses already mapped by the taken over DTLB.
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	 */
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	set kernel_image_start, %g7
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	! write ITLB tag of context 1
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	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
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	set VA_DMMU_TAG_ACCESS, %g2
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	stxa %g1, [%g2] ASI_IMMU
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	flush %g7
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	! write ITLB data and install the temporary mapping in context 1
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	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
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	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
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	flush %g7
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- 
 
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	! switch to context 1
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	set MEM_CONTEXT_TEMP, %g1
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	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
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	flush %g7
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- 
 
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	! demap context 0
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	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
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	stxa %g0, [%g1] ASI_IMMU_DEMAP
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	flush %g7
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	! write ITLB tag of context 0
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	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
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	set VA_DMMU_TAG_ACCESS, %g2
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	stxa %g1, [%g2] ASI_IMMU
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	flush %g7
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	! write ITLB data and install the permanent kernel mapping in context 0
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	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
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	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
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	flush %g7
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	! switch to context 0
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	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
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	flush %g7
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	! ensure nucleus mapping
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	wrpr %g0, 1, %tl
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	! set context 1 in the primary context register
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	set MEM_CONTEXT_TEMP, %g1
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	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
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	flush %g7
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 202 
	! demap context 1
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	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
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 204 
	stxa %g0, [%g1] ASI_IMMU_DEMAP
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 205 
	flush %g7
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- 
 
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	! set context 0 in the primary context register
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 208 
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
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 209 
	flush %g7
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 210
- 
 
 211 
	! set TL back to 0
- 
 
 212 
	wrpr %g0, 0, %tl
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 213
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	call main_bsp
 214 
	call main_bsp
88 
	nop
 215 
	nop
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 216 
 
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	/* Not reached. */
 217 
	/* Not reached. */
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