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#include <arch.h>
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#include <arch.h>
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <config.h>
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#include <config.h>
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#include <mm/tlb.h>
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#include <mm/tlb.h>
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#include <arch/mm/cache.h>
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#include <arch/interrupt.h>
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#include <arch/interrupt.h>
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#include <arch/trap/interrupt.h>
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#include <arch/trap/interrupt.h>
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#include <arch/barrier.h>
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#include <arch/barrier.h>
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#include <preemption.h>
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#include <preemption.h>
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#include <time/delay.h>
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#include <time/delay.h>
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    do {
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    do {
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        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t)
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        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t)
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            func);
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            func);
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        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
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        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
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        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
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        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
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        asi_u64_write(ASI_UDB_INTR_W, (mid <<
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        asi_u64_write(ASI_UDB_INTR_W,
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            INTR_VEC_DISPATCH_MID_SHIFT) | ASI_UDB_INTR_W_DISPATCH,
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            (mid << INTR_VEC_DISPATCH_MID_SHIFT) |
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            0);
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            ASI_UDB_INTR_W_DISPATCH, 0);
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        membar();
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        membar();
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        do {
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        do {
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            status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
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            status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
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    switch (ipi) {
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    switch (ipi) {
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    case IPI_TLB_SHOOTDOWN:
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    case IPI_TLB_SHOOTDOWN:
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        func = tlb_shootdown_ipi_recv;
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        func = tlb_shootdown_ipi_recv;
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        break;
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        break;
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#if (defined(CONFIG_SMP) && (defined(CONFIG_VIRT_IDX_DCACHE)))
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    case IPI_DCACHE_SHOOTDOWN:
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        func = dcache_shootdown_ipi_recv;
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        break;
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#endif
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    default:
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    default:
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        panic("Unknown IPI (%d).\n", ipi);
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        panic("Unknown IPI (%d).\n", ipi);
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        break;
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        break;
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    }
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    }
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