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| Rev 2089 | Rev 2141 | ||
|---|---|---|---|
| Line 60... | Line 60... | ||
| 60 | 60 | ||
| 61 | int as_constructor_arch(as_t *as, int flags) |
61 | int as_constructor_arch(as_t *as, int flags) |
| 62 | { |
62 | { |
| 63 | #ifdef CONFIG_TSB |
63 | #ifdef CONFIG_TSB |
| 64 | int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
64 | int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
| 65 | sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
65 | sizeof(tsb_entry_t)) >> MMU_FRAME_WIDTH); |
| 66 | uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
66 | uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
| 67 | 67 | ||
| 68 | if (!tsb) |
68 | if (!tsb) |
| 69 | return -1; |
69 | return -1; |
| 70 | 70 | ||
| 71 | as->arch.itsb = (tsb_entry_t *) tsb; |
71 | as->arch.itsb = (tsb_entry_t *) tsb; |
| 72 | as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * |
72 | as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * |
| 73 | sizeof(tsb_entry_t)); |
73 | sizeof(tsb_entry_t)); |
| 74 | memsetb((uintptr_t) as->arch.itsb, (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) |
74 | memsetb((uintptr_t) as->arch.itsb, |
| 75 | * sizeof(tsb_entry_t), 0); |
75 | (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); |
| 76 | #endif |
76 | #endif |
| 77 | return 0; |
77 | return 0; |
| 78 | } |
78 | } |
| 79 | 79 | ||
| 80 | int as_destructor_arch(as_t *as) |
80 | int as_destructor_arch(as_t *as) |
| 81 | { |
81 | { |
| 82 | #ifdef CONFIG_TSB |
82 | #ifdef CONFIG_TSB |
| 83 | count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
83 | count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
| 84 | sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
84 | sizeof(tsb_entry_t)) >> MMU_FRAME_WIDTH; |
| 85 | frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
85 | frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
| 86 | return cnt; |
86 | return cnt; |
| 87 | #else |
87 | #else |
| 88 | return 0; |
88 | return 0; |
| 89 | #endif |
89 | #endif |
| Line 137... | Line 137... | ||
| 137 | 137 | ||
| 138 | ASSERT(as->arch.itsb && as->arch.dtsb); |
138 | ASSERT(as->arch.itsb && as->arch.dtsb); |
| 139 | 139 | ||
| 140 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
140 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
| 141 | 141 | ||
| 142 | if (!overlaps(tsb, 8 * PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
142 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
| 143 | /* |
143 | /* |
| 144 | * TSBs were allocated from memory not covered |
144 | * TSBs were allocated from memory not covered |
| 145 | * by the locked 4M kernel DTLB entry. We need |
145 | * by the locked 4M kernel DTLB entry. We need |
| 146 | * to map both TSBs explicitly. |
146 | * to map both TSBs explicitly. |
| 147 | */ |
147 | */ |
| Line 156... | Line 156... | ||
| 156 | 156 | ||
| 157 | tsb_base.value = 0; |
157 | tsb_base.value = 0; |
| 158 | tsb_base.size = TSB_SIZE; |
158 | tsb_base.size = TSB_SIZE; |
| 159 | tsb_base.split = 0; |
159 | tsb_base.split = 0; |
| 160 | 160 | ||
| 161 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH; |
161 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; |
| 162 | itsb_base_write(tsb_base.value); |
162 | itsb_base_write(tsb_base.value); |
| 163 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH; |
163 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH; |
| 164 | dtsb_base_write(tsb_base.value); |
164 | dtsb_base_write(tsb_base.value); |
| 165 | #endif |
165 | #endif |
| 166 | } |
166 | } |
| 167 | 167 | ||
| 168 | /** Perform sparc64-specific tasks when an address space is removed from the |
168 | /** Perform sparc64-specific tasks when an address space is removed from the |
| Line 187... | Line 187... | ||
| 187 | 187 | ||
| 188 | ASSERT(as->arch.itsb && as->arch.dtsb); |
188 | ASSERT(as->arch.itsb && as->arch.dtsb); |
| 189 | 189 | ||
| 190 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
190 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
| 191 | 191 | ||
| 192 | if (!overlaps(tsb, 8 * PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
192 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
| 193 | /* |
193 | /* |
| 194 | * TSBs were allocated from memory not covered |
194 | * TSBs were allocated from memory not covered |
| 195 | * by the locked 4M kernel DTLB entry. We need |
195 | * by the locked 4M kernel DTLB entry. We need |
| 196 | * to demap the entry installed by as_install_arch(). |
196 | * to demap the entry installed by as_install_arch(). |
| 197 | */ |
197 | */ |