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Line 47... | Line 47... | ||
47 | #include <mm/frame.h> |
47 | #include <mm/frame.h> |
48 | #include <bitops.h> |
48 | #include <bitops.h> |
49 | #include <macros.h> |
49 | #include <macros.h> |
50 | #endif /* CONFIG_TSB */ |
50 | #endif /* CONFIG_TSB */ |
51 | 51 | ||
52 | #ifdef CONFIG_VIRT_IDX_DCACHE |
- | |
53 | #include <arch/mm/cache.h> |
- | |
54 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
- | |
55 | - | ||
56 | /** Architecture dependent address space init. */ |
52 | /** Architecture dependent address space init. */ |
57 | void as_arch_init(void) |
53 | void as_arch_init(void) |
58 | { |
54 | { |
59 | if (config.cpu_active == 1) { |
55 | if (config.cpu_active == 1) { |
60 | as_operations = &as_ht_operations; |
56 | as_operations = &as_ht_operations; |
Line 160... | Line 156... | ||
160 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH; |
156 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH; |
161 | itsb_base_write(tsb_base.value); |
157 | itsb_base_write(tsb_base.value); |
162 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH; |
158 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH; |
163 | dtsb_base_write(tsb_base.value); |
159 | dtsb_base_write(tsb_base.value); |
164 | #endif |
160 | #endif |
165 | #ifdef CONFIG_VIRT_IDX_DCACHE |
- | |
166 | if (as->dcache_flush_on_install) { |
- | |
167 | /* |
- | |
168 | * Some mappings in this address space are illegal address |
- | |
169 | * aliases. Upon their creation, the dcache_flush_on_install |
- | |
170 | * flag was set. |
- | |
171 | * |
- | |
172 | * We are now obliged to flush the D-cache in order to guarantee |
- | |
173 | * that there will be at most one cache line for each address |
- | |
174 | * alias. |
- | |
175 | * |
- | |
176 | * This flush performs a cleanup after another address space in |
- | |
177 | * which the alias might have existed. |
- | |
178 | */ |
- | |
179 | dcache_flush(); |
- | |
180 | } |
- | |
181 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
- | |
182 | } |
161 | } |
183 | 162 | ||
184 | /** Perform sparc64-specific tasks when an address space is removed from the processor. |
163 | /** Perform sparc64-specific tasks when an address space is removed from the processor. |
185 | * |
164 | * |
186 | * Demap TSBs. |
165 | * Demap TSBs. |
Line 211... | Line 190... | ||
211 | * to demap the entry installed by as_install_arch(). |
190 | * to demap the entry installed by as_install_arch(). |
212 | */ |
191 | */ |
213 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
192 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
214 | } |
193 | } |
215 | #endif |
194 | #endif |
216 | #ifdef CONFIG_VIRT_IDX_DCACHE |
- | |
217 | if (as->dcache_flush_on_deinstall) { |
- | |
218 | /* |
- | |
219 | * Some mappings in this address space are illegal address |
- | |
220 | * aliases. Upon their creation, the dcache_flush_on_deinstall |
- | |
221 | * flag was set. |
- | |
222 | * |
- | |
223 | * We are now obliged to flush the D-cache in order to guarantee |
- | |
224 | * that there will be at most one cache line for each address |
- | |
225 | * alias. |
- | |
226 | * |
- | |
227 | * This flush performs a cleanup after this address space. It is |
- | |
228 | * necessary because other address spaces that contain the same |
- | |
229 | * alias are not necessarily aware of the need to carry out the |
- | |
230 | * cache flush. The only address spaces that are aware of it are |
- | |
231 | * those that created the illegal alias. |
- | |
232 | */ |
- | |
233 | dcache_flush(); |
- | |
234 | } |
- | |
235 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
- | |
236 | } |
195 | } |
237 | 196 | ||
238 | /** @} |
197 | /** @} |
239 | */ |
198 | */ |