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Line 45... | Line 45... | ||
45 | #include <synch/mutex.h> |
45 | #include <synch/mutex.h> |
46 | #include <arch/asm.h> |
46 | #include <arch/asm.h> |
47 | #include <mm/frame.h> |
47 | #include <mm/frame.h> |
48 | #include <bitops.h> |
48 | #include <bitops.h> |
49 | #include <macros.h> |
49 | #include <macros.h> |
50 | #endif |
50 | #endif /* CONFIG_TSB */ |
- | 51 | ||
- | 52 | #ifdef CONFIG_VIRT_IDX_DCACHE |
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- | 53 | #include <arch/mm/cache.h> |
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- | 54 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
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51 | 55 | ||
52 | /** Architecture dependent address space init. */ |
56 | /** Architecture dependent address space init. */ |
53 | void as_arch_init(void) |
57 | void as_arch_init(void) |
54 | { |
58 | { |
55 | if (config.cpu_active == 1) { |
59 | if (config.cpu_active == 1) { |
Line 156... | Line 160... | ||
156 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH; |
160 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH; |
157 | itsb_base_write(tsb_base.value); |
161 | itsb_base_write(tsb_base.value); |
158 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH; |
162 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH; |
159 | dtsb_base_write(tsb_base.value); |
163 | dtsb_base_write(tsb_base.value); |
160 | #endif |
164 | #endif |
- | 165 | #ifdef CONFIG_VIRT_IDX_DCACHE |
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- | 166 | if (as->dcache_flush_on_install) { |
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- | 167 | /* |
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- | 168 | * Some mappings in this address space are illegal address |
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- | 169 | * aliases. Upon their creation, the flush_dcache_on_install |
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- | 170 | * flag was set. |
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- | 171 | * |
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- | 172 | * We are now obliged to flush the D-cache in order to guarantee |
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- | 173 | * that there will be at most one cache line for each address |
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- | 174 | * alias. |
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- | 175 | * |
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- | 176 | * This flush performs a cleanup after another address space in |
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- | 177 | * which the alias might have existed. |
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- | 178 | */ |
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- | 179 | dcache_flush(); |
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- | 180 | } |
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- | 181 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
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161 | } |
182 | } |
162 | 183 | ||
163 | /** Perform sparc64-specific tasks when an address space is removed from the processor. |
184 | /** Perform sparc64-specific tasks when an address space is removed from the processor. |
164 | * |
185 | * |
165 | * Demap TSBs. |
186 | * Demap TSBs. |
Line 190... | Line 211... | ||
190 | * to demap the entry installed by as_install_arch(). |
211 | * to demap the entry installed by as_install_arch(). |
191 | */ |
212 | */ |
192 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
213 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
193 | } |
214 | } |
194 | #endif |
215 | #endif |
- | 216 | #ifdef CONFIG_VIRT_IDX_DCACHE |
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- | 217 | if (as->dcache_flush_on_deinstall) { |
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- | 218 | /* |
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- | 219 | * Some mappings in this address space are illegal address |
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- | 220 | * aliases. Upon their creation, the flush_dcache_on_deinstall |
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- | 221 | * flag was set. |
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- | 222 | * |
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- | 223 | * We are now obliged to flush the D-cache in order to guarantee |
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- | 224 | * that there will be at most one cache line for each address |
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- | 225 | * alias. |
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- | 226 | * |
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- | 227 | * This flush performs a cleanup after this address space. It is |
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- | 228 | * necessary because other address spaces that contain the same |
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- | 229 | * alias are not necessarily aware of the need to carry out the |
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- | 230 | * cache flush. The only address spaces that are aware of it are |
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- | 231 | * those that created the illegal alias. |
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- | 232 | */ |
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- | 233 | dcache_flush(); |
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- | 234 | } |
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- | 235 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
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195 | } |
236 | } |
196 | 237 | ||
197 | /** @} |
238 | /** @} |
198 | */ |
239 | */ |