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#include <arch/register.h>
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#include <arch/register.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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void fpu_context_save(fpu_context_t *fctx)
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void fpu_context_save(fpu_context_t *fctx)
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{
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{
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    __asm__ volatile (
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    asm volatile (
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        "std %%f0, %0\n"
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        "std %%f0, %0\n"
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        "std %%f2, %1\n"
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        "std %%f2, %1\n"
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        "std %%f4, %2\n"
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        "std %%f4, %2\n"
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        "std %%f6, %3\n"
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        "std %%f6, %3\n"
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        "std %%f8, %4\n"
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        "std %%f8, %4\n"
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    /*
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    /*
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     * We need to split loading of the floating-point registers because
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     * We need to split loading of the floating-point registers because
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     * GCC (4.1.1) can't handle more than 30 operands in one asm statement.
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     * GCC (4.1.1) can't handle more than 30 operands in one asm statement.
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     */
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     */
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    __asm__ volatile (
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    asm volatile (
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        "std %%f32, %0\n"
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        "std %%f32, %0\n"
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        "std %%f34, %1\n"
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        "std %%f34, %1\n"
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        "std %%f36, %2\n"
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        "std %%f36, %2\n"
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        "std %%f38, %3\n"
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        "std %%f38, %3\n"
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        "std %%f40, %4\n"
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        "std %%f40, %4\n"
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          "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]),
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          "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]),
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          "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]),
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          "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]),
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          "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])
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          "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])
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    );
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    );
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    __asm__ volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr));
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    asm volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr));
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}
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}
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void fpu_context_restore(fpu_context_t *fctx)
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void fpu_context_restore(fpu_context_t *fctx)
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{
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{
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    __asm__ volatile (
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    asm volatile (
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        "ldd %0, %%f0\n"
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        "ldd %0, %%f0\n"
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        "ldd %1, %%f2\n"
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        "ldd %1, %%f2\n"
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        "ldd %2, %%f4\n"
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        "ldd %2, %%f4\n"
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        "ldd %3, %%f6\n"
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        "ldd %3, %%f6\n"
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        "ldd %4, %%f8\n"
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        "ldd %4, %%f8\n"
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    /*
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    /*
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     * We need to split loading of the floating-point registers because
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     * We need to split loading of the floating-point registers because
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     * GCC (4.1.1) can't handle more than 30 operands in one asm statement.
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     * GCC (4.1.1) can't handle more than 30 operands in one asm statement.
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     */
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     */
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    __asm__ volatile (
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    asm volatile (
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        "ldd %0, %%f32\n"
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        "ldd %0, %%f32\n"
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        "ldd %1, %%f34\n"
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        "ldd %1, %%f34\n"
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        "ldd %2, %%f36\n"
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        "ldd %2, %%f36\n"
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        "ldd %3, %%f38\n"
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        "ldd %3, %%f38\n"
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        "ldd %4, %%f40\n"
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        "ldd %4, %%f40\n"
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          "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]),
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          "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]),
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          "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]),
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          "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]),
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          "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])
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          "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])
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    );
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    );
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    __asm__ volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr));
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    asm volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr));
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}
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}
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void fpu_enable(void)
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void fpu_enable(void)
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{
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{
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    pstate_reg_t pstate;
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    pstate_reg_t pstate;