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Rev 1899 Rev 2044
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{
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{
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    tick_compare_reg_t compare;
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    tick_compare_reg_t compare;
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    interrupt_register(14, "tick_int", tick_interrupt);
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    interrupt_register(14, "tick_int", tick_interrupt);
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    compare.int_dis = false;
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    compare.int_dis = false;
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    compare.tick_cmpr = CPU->arch.clock_frequency/HZ;
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    compare.tick_cmpr = CPU->arch.clock_frequency / HZ;
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    CPU->arch.next_tick_cmpr = compare.tick_cmpr;
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    tick_compare_write(compare.value);
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    tick_compare_write(compare.value);
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    tick_write(0);
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    tick_write(0);
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}
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}
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/** Process tick interrupt.
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/** Process tick interrupt.
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 * @param istate Interrupted state.
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 * @param istate Interrupted state.
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 */
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 */
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void tick_interrupt(int n, istate_t *istate)
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void tick_interrupt(int n, istate_t *istate)
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{
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{
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    softint_reg_t softint, clear;
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    softint_reg_t softint, clear;
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    uint64_t next, compare, start, stop;
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    uint64_t drift;
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    softint.value = softint_read();
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    softint.value = softint_read();
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    /*
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    /*
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     * Make sure we are servicing interrupt_level_14
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     * Make sure we are servicing interrupt_level_14
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    clear.value = 0;
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    clear.value = 0;
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    clear.tick_int = 1;
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    clear.tick_int = 1;
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    clear_softint_write(clear.value);
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    clear_softint_write(clear.value);
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    /*
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    /*
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     * Restart counter.
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     * Reprogram the compare register.
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     * For now, we can ignore the potential of the registers to overflow.
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     * On a 360MHz Ultra 60, the 63-bit compare counter will overflow in
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     * about 812 years. If there was a 2GHz UltraSPARC computer, it would
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     * overflow only in 146 years.
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     */
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     */
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    compare = CPU->arch.clock_frequency/HZ;
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    drift = tick_read() - CPU->arch.next_tick_cmpr;
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    start = tick_read();
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    next = start - compare;
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    while (next >= compare - TICK_RESTART_TIME) {
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    while (drift > CPU->arch.clock_frequency / HZ) {
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        next -= compare;
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        drift -= CPU->arch.clock_frequency / HZ;
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        CPU->missed_clock_ticks++;
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        CPU->missed_clock_ticks++;
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    }
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    }
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    CPU->arch.next_tick_cmpr = tick_read() + (CPU->arch.clock_frequency / HZ)
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    stop = tick_read();
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        - drift;
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    tick_write(next + (stop - start));
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    tick_compare_write(CPU->arch.next_tick_cmpr);
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    clock();
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    clock();
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}
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}
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/** @}
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/** @}
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 */
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 */