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#define OBIO_IMR(ino)   (OBIO_IMR_BASE + ((ino) & INO_MASK))
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#define OBIO_IMR(ino)   (OBIO_IMR_BASE + ((ino) & INO_MASK))
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#define OBIO_CIR_BASE   0x300
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#define OBIO_CIR_BASE   0x300
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#define OBIO_CIR(ino)   (OBIO_CIR_BASE + ((ino) & INO_MASK))
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#define OBIO_CIR(ino)   (OBIO_CIR_BASE + ((ino) & INO_MASK))
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static void obio_enable_interrupt(pci_t *pci, int inr);
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static void obio_enable_interrupt(pci_t *, int);
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static void obio_clear_interrupt(pci_t *pci, int inr);
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static void obio_clear_interrupt(pci_t *, int);
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static pci_t *pci_sabre_init(ofw_tree_node_t *node);
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static pci_t *pci_sabre_init(ofw_tree_node_t *);
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static pci_t *pci_psycho_init(ofw_tree_node_t *node);
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static pci_t *pci_psycho_init(ofw_tree_node_t *);
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/** PCI operations for Sabre model. */
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/** PCI operations for Sabre model. */
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static pci_operations_t pci_sabre_ops = {
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static pci_operations_t pci_sabre_ops = {
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    .enable_interrupt = obio_enable_interrupt,
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    .enable_interrupt = obio_enable_interrupt,
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    .clear_interrupt = obio_clear_interrupt
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    .clear_interrupt = obio_clear_interrupt
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{
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{
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    ASSERT(pci->op && pci->op->enable_interrupt);
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    ASSERT(pci->op && pci->op->enable_interrupt);
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    pci->op->enable_interrupt(pci, inr);
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    pci->op->enable_interrupt(pci, inr);
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}
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}
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void pci_clear_interrupt(pci_t *pci, int inr)
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void pci_clear_interrupt(void *pcip, int inr)
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{
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{
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    pci_t *pci = (pci_t *)pcip;
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    ASSERT(pci->op && pci->op->clear_interrupt);
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    ASSERT(pci->op && pci->op->clear_interrupt);
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    pci->op->clear_interrupt(pci, inr);
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    pci->op->clear_interrupt(pci, inr);
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}
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}
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/** @}
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/** @}