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Rev 1946 Rev 1984
Line 49... Line 49...
49 
#define PCI_SABRE_REGS_REG  0
 49 
#define PCI_SABRE_REGS_REG  0
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 50 
 
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#define PCI_SABRE_IMAP_BASE 0x200
 51 
#define PCI_SABRE_IMAP_BASE 0x200
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#define PCI_SABRE_ICLR_BASE 0x300
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#define PCI_SABRE_ICLR_BASE 0x300
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 53 
 
- 
 
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#define PCI_PSYCHO_REGS_REG 2  
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#define PCI_PSYCHO_IMAP_BASE    0x200
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#define PCI_PSYCHO_ICLR_BASE    0x300  
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static pci_t *pci_sabre_init(ofw_tree_node_t *node);
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static pci_t *pci_sabre_init(ofw_tree_node_t *node);
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static void pci_sabre_enable_interrupt(pci_t *pci, int inr);
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static void pci_sabre_enable_interrupt(pci_t *pci, int inr);
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static void pci_sabre_clear_interrupt(pci_t *pci, int inr);
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static void pci_sabre_clear_interrupt(pci_t *pci, int inr);
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static pci_t *pci_psycho_init(ofw_tree_node_t *node);
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static void pci_psycho_enable_interrupt(pci_t *pci, int inr);
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static void pci_psycho_clear_interrupt(pci_t *pci, int inr);
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/** PCI operations for Sabre model. */
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/** PCI operations for Sabre model. */
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static pci_operations_t pci_sabre_ops = {
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static pci_operations_t pci_sabre_ops = {
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    .enable_interrupt = pci_sabre_enable_interrupt,
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    .enable_interrupt = pci_sabre_enable_interrupt,
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    .clear_interrupt = pci_sabre_clear_interrupt
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    .clear_interrupt = pci_sabre_clear_interrupt
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};
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};
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/** PCI operations for Psycho model. */
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static pci_operations_t pci_psycho_ops = {
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    .enable_interrupt = pci_psycho_enable_interrupt,
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    .clear_interrupt = pci_psycho_clear_interrupt
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};
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/** Initialize PCI controller (model Sabre). */
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/** Initialize PCI controller (model Sabre).
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 *
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 * @param node OpenFirmware device tree node of the Sabre.
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 *
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 * @return Address of the initialized PCI structure.
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 */
65 
pci_t *pci_sabre_init(ofw_tree_node_t *node)
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pci_t *pci_sabre_init(ofw_tree_node_t *node)
66 
{
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{
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    pci_t *pci;
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    pci_t *pci;
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    ofw_tree_property_t *prop;
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    ofw_tree_property_t *prop;
69 
 
 88 
 
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    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_SABRE_REGS_REG].size);
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    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_SABRE_REGS_REG].size);
94 
 
 113 
 
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    return pci;
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    return pci;
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}
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}
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/** Initialize the Psycho PCI controller.
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 119 
 *
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 * @param node OpenFirmware device tree node of the Psycho.
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 *
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 * @return Address of the initialized PCI structure.
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 123 
 */
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pci_t *pci_psycho_init(ofw_tree_node_t *node)
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{
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    pci_t *pci;
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    ofw_tree_property_t *prop;
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    /*
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     * Get registers.
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     */
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    prop = ofw_tree_getprop(node, "reg");
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    if (!prop || !prop->value)
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        return NULL;
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    ofw_upa_reg_t *reg = prop->value;
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    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
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    if (regs < PCI_PSYCHO_REGS_REG + 1)
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        return NULL;
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    uintptr_t paddr;
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    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_PSYCHO_REGS_REG], &paddr))
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        return NULL;
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    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
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 147 
    if (!pci)
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        return NULL;
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    pci->model = PCI_PSYCHO;
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    pci->op = &pci_psycho_ops;
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    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_PSYCHO_REGS_REG].size);
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    return pci;
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}
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 156 
 
98 
void pci_sabre_enable_interrupt(pci_t *pci, int inr)
 157 
void pci_sabre_enable_interrupt(pci_t *pci, int inr)
99 
{
 158 
{
100 
    pci->reg[PCI_SABRE_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
 159 
    pci->reg[PCI_SABRE_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
101 
}
 160 
}
102 
 
 161 
 
103 
void pci_sabre_clear_interrupt(pci_t *pci, int inr)
 162 
void pci_sabre_clear_interrupt(pci_t *pci, int inr)
104 
{
 163 
{
105 
    pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0;
 164 
    pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0;
106 
}
 165 
}
107 
 
 166 
 
- 
 
 167 
void pci_psycho_enable_interrupt(pci_t *pci, int inr)
- 
 
 168 
{
- 
 
 169 
    pci->reg[PCI_PSYCHO_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
- 
 
 170 
}
- 
 
 171 
 
- 
 
 172 
void pci_psycho_clear_interrupt(pci_t *pci, int inr)
- 
 
 173 
{
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 174 
    pci->reg[PCI_PSYCHO_ICLR_BASE + (inr & INO_MASK)] = 0;
- 
 
 175 
}
- 
 
 176 
 
108 
/** Initialize PCI controller. */
 177 
/** Initialize PCI controller. */
109 
pci_t *pci_init(ofw_tree_node_t *node)
 178 
pci_t *pci_init(ofw_tree_node_t *node)
110 
{
 179 
{
111 
    ofw_tree_property_t *prop;
 180 
    ofw_tree_property_t *prop;
112 
 
 181 
 
Line 126... Line 195...
126 
        /*
 195 
        /*
127 
         * PCI controller Sabre.
 196 
         * PCI controller Sabre.
128 
         * This model is found on UltraSPARC IIi based machines.
 197 
         * This model is found on UltraSPARC IIi based machines.
129 
         */
 198 
         */
130 
        return pci_sabre_init(node);
 199 
        return pci_sabre_init(node);
- 
 
 200 
    } else if (strcmp(prop->value, "SUNW,psycho") == 0) {
- 
 
 201 
        /*
- 
 
 202 
         * PCI controller Psycho.
- 
 
 203 
         * Used on UltraSPARC II based processors, for instance,
- 
 
 204 
         * on Ultra 60.
- 
 
 205 
         */
- 
 
 206 
        return pci_psycho_init(node);
131 
    } else {
 207 
    } else {
132 
        /*
 208 
        /*
133 
         * Unsupported model.
 209 
         * Unsupported model.
134 
         */
 210 
         */
135 
        printf("Unsupported PCI controller model (%s).\n", prop->value);
 211 
        printf("Unsupported PCI controller model (%s).\n", prop->value);