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/**
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/**
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 * I suspect this must be hardcoded in the FHC.
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 * I suspect this must be hardcoded in the FHC.
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 * If it is not, than we can read all IMAP registers
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 * If it is not, than we can read all IMAP registers
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 * and get the complete mapping.
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 * and get the complete mapping.
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 */
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 */
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#define FHC_UART_INO    0x39   
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#define FHC_UART_INR    0x39   
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#define FHC_UART_IMAP   0x0
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#define FHC_UART_IMAP   0x0
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#define FHC_UART_ICLR   0x4
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#define FHC_UART_ICLR   0x4
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#define UART_IMAP_REG   4
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#define UART_IMAP_REG   4
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    fhc->uart_imap = (uint32_t *) hw_map(paddr, reg->size);
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    fhc->uart_imap = (uint32_t *) hw_map(paddr, reg->size);
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    return fhc;
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    return fhc;
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}
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}
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void fhc_enable_interrupt(fhc_t *fhc, int ino)
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void fhc_enable_interrupt(fhc_t *fhc, int inr)
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{
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{
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    switch (ino) {
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    switch (inr) {
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    case FHC_UART_INO:
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    case FHC_UART_INR:
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        fhc->uart_imap[FHC_UART_ICLR] = 0x0;
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        fhc->uart_imap[FHC_UART_ICLR] = 0x0;
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        fhc->uart_imap[FHC_UART_IMAP] = 0x80000000;
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        fhc->uart_imap[FHC_UART_IMAP] = 0x80000000;
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        break;
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        break;
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    default:
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    default:
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        panic("Unexpected INO (%d)\n", ino);
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        panic("Unexpected INR (%d)\n", inr);
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        break;
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        break;
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    }
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    }
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}
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}
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void fhc_clear_interrupt(fhc_t *fhc, int ino)
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void fhc_clear_interrupt(fhc_t *fhc, int inr)
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{
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{
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    ASSERT(fhc->uart_imap);
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    ASSERT(fhc->uart_imap);
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    switch (ino) {
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    switch (inr) {
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    case FHC_UART_INO:
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    case FHC_UART_INR:
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        fhc->uart_imap[FHC_UART_ICLR] = 0;
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        fhc->uart_imap[FHC_UART_ICLR] = 0;
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        break;
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        break;
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    default:
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    default:
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        panic("Unexpected INO (%d)\n", ino);
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        panic("Unexpected INR (%d)\n", inr);
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        break;
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        break;
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    }
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    }
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}
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}
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/** @}
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/** @}