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| Rev 1875 | Rev 1909 | ||
|---|---|---|---|
| Line 39... | Line 39... | ||
| 39 | * publicly available. |
39 | * publicly available. |
| 40 | */ |
40 | */ |
| 41 | 41 | ||
| 42 | #include <arch/drivers/fhc.h> |
42 | #include <arch/drivers/fhc.h> |
| 43 | #include <arch/mm/page.h> |
43 | #include <arch/mm/page.h> |
| - | 44 | #include <mm/slab.h> |
|
| 44 | #include <arch/types.h> |
45 | #include <arch/types.h> |
| 45 | #include <typedefs.h> |
46 | #include <typedefs.h> |
| 46 | - | ||
| - | 47 | #include <genarch/ofw/ofw_tree.h> |
|
| 47 | #include <genarch/kbd/z8530.h> |
48 | #include <genarch/kbd/z8530.h> |
| 48 | 49 | ||
| 49 | volatile uint32_t *fhc = NULL; |
50 | fhc_t *central_fhc = NULL; |
| 50 | 51 | ||
| - | 52 | /** |
|
| 51 | #define FHC_UART_ADDR 0x1fff8808000ULL /* hardcoded for Simics simulation */ |
53 | * I suspect this must be hardcoded in the FHC. |
| - | 54 | * If it is not, than we can read all IMAP registers |
|
| - | 55 | * and get the complete mapping. |
|
| - | 56 | */ |
|
| - | 57 | #define FHC_UART_INO 0x39 |
|
| 52 | 58 | ||
| 53 | #define FHC_UART_IMAP 0x0 |
59 | #define FHC_UART_IMAP 0x0 |
| 54 | #define FHC_UART_ICLR 0x4 |
60 | #define FHC_UART_ICLR 0x4 |
| 55 | 61 | ||
| - | 62 | #define UART_IMAP_REG 4 |
|
| - | 63 | ||
| 56 | void fhc_init(void) |
64 | fhc_t *fhc_init(ofw_tree_node_t *node) |
| 57 | { |
65 | { |
| - | 66 | fhc_t *fhc; |
|
| 58 | fhc = (void *) hw_map(FHC_UART_ADDR, PAGE_SIZE); |
67 | ofw_tree_property_t *prop; |
| 59 | 68 | ||
| - | 69 | prop = ofw_tree_getprop(node, "reg"); |
|
| - | 70 | ||
| 60 | fhc[FHC_UART_ICLR] = 0; |
71 | if (!prop || !prop->value) |
| - | 72 | return NULL; |
|
| - | 73 | ||
| - | 74 | count_t regs = prop->size / sizeof(ofw_central_reg_t); |
|
| 61 | fhc[FHC_UART_IMAP] = 0x80000000; |
75 | if (regs + 1 < UART_IMAP_REG) |
| - | 76 | return NULL; |
|
| - | 77 | ||
| - | 78 | ofw_central_reg_t *reg = &((ofw_central_reg_t *) prop->value)[UART_IMAP_REG]; |
|
| - | 79 | ||
| - | 80 | uintptr_t paddr; |
|
| - | 81 | if (!ofw_central_apply_ranges(node->parent, reg, &paddr)) |
|
| - | 82 | return NULL; |
|
| - | 83 | ||
| - | 84 | fhc = (fhc_t *) malloc(sizeof(fhc_t), FRAME_ATOMIC); |
|
| - | 85 | if (!fhc) |
|
| - | 86 | return NULL; |
|
| - | 87 | ||
| - | 88 | fhc->uart_imap = (uint32_t *) hw_map(paddr, reg->size); |
|
| - | 89 | ||
| - | 90 | return fhc; |
|
| 62 | } |
91 | } |
| 63 | 92 | ||
| 64 | void fhc_uart_reset(void) |
93 | void fhc_enable_interrupt(fhc_t *fhc, int ino) |
| 65 | { |
94 | { |
| - | 95 | switch (ino) { |
|
| - | 96 | case FHC_UART_INO: |
|
| - | 97 | fhc->uart_imap[FHC_UART_ICLR] = 0x0; |
|
| - | 98 | fhc->uart_imap[FHC_UART_IMAP] = 0x80000000; |
|
| - | 99 | break; |
|
| - | 100 | default: |
|
| - | 101 | panic("Unexpected INO (%d)\n", ino); |
|
| - | 102 | break; |
|
| - | 103 | } |
|
| - | 104 | } |
|
| - | 105 | ||
| - | 106 | void fhc_clear_interrupt(fhc_t *fhc, int ino) |
|
| - | 107 | { |
|
| - | 108 | ASSERT(fhc->uart_imap); |
|
| - | 109 | ||
| - | 110 | switch (ino) { |
|
| - | 111 | case FHC_UART_INO: |
|
| 66 | fhc[FHC_UART_ICLR] = 0; |
112 | fhc->uart_imap[FHC_UART_ICLR] = 0; |
| - | 113 | break; |
|
| - | 114 | default: |
|
| - | 115 | panic("Unexpected INO (%d)\n", ino); |
|
| - | 116 | break; |
|
| - | 117 | } |
|
| 67 | } |
118 | } |
| 68 | 119 | ||
| 69 | /** @} |
120 | /** @} |
| 70 | */ |
121 | */ |