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#include <arch/mm/tlb.h>
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#include <arch/mm/tlb.h>
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#include <arch/mm/mmu.h>
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#include <arch/mm/mmu.h>
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#include <arch/mm/tte.h>
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#include <arch/mm/tte.h>
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#include <arch/trap/regwin.h>
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#include <arch/trap/regwin.h>
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- 
 
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#ifdef CONFIG_TSB
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#include <arch/mm/tsb.h>
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#endif
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#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
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#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
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#define TT_FAST_DATA_ACCESS_MMU_MISS        0x68
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#define TT_FAST_DATA_ACCESS_MMU_MISS        0x68
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#define TT_FAST_DATA_ACCESS_PROTECTION      0x6c
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#define TT_FAST_DATA_ACCESS_PROTECTION      0x6c
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#define FAST_MMU_HANDLER_SIZE           128
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#define FAST_MMU_HANDLER_SIZE           128
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.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
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.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
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    /*
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    /*
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     * First, try to refill TLB from TSB.
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     * First, try to refill TLB from TSB.
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     */
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     */
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    ! TODO
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#ifdef CONFIG_TSB
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    ldxa [%g0] ASI_IMMU, %g1            ! read TSB Tag Target Register
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    ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2    ! read TSB 8K Pointer
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    ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4        ! 16-byte atomic load into %g4 and %g5
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    cmp %g1, %g4                    ! is this the entry we are looking for?
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    bne,pn %xcc, 0f
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    nop
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    stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG        ! copy mapping from ITSB to ITLB
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    retry
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#endif
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0:
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
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    PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
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.endm
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.endm
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.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
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.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
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    /*
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    /*
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     * First, try to refill TLB from TSB.
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     * First, try to refill TLB from TSB.
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     */
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     */
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#ifdef CONFIG_TSB
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    ldxa [%g0] ASI_DMMU, %g1            ! read TSB Tag Target Register
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    srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this kernel miss?
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    brz,pn %g2, 0f
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    ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3    ! read TSB 8K Pointer
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    ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4        ! 16-byte atomic load into %g4 and %g5
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    cmp %g1, %g4                    ! is this the entry we are looking for?
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    bne,pn %xcc, 0f
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    nop
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    stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG        ! copy mapping from DTSB to DTLB
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    ! TODO
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    retry
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#endif
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    /*
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    /*
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     * Second, test if it is the portion of the kernel address space
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     * Second, test if it is the portion of the kernel address space
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     * which is faulting. If that is the case, immediately create
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     * which is faulting. If that is the case, immediately create
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     * identity mapping for that page in DTLB. VPN 0 is excluded from
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     * identity mapping for that page in DTLB. VPN 0 is excluded from
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     * this treatment.
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     * this treatment.
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     *
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     *
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     * Note that branch-delay slots are used in order to save space.
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     * Note that branch-delay slots are used in order to save space.
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     */
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     */
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0:
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    mov VA_DMMU_TAG_ACCESS, %g1
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    mov VA_DMMU_TAG_ACCESS, %g1
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    ldxa [%g1] ASI_DMMU, %g1            ! read the faulting Context and VPN
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    ldxa [%g1] ASI_DMMU, %g1            ! read the faulting Context and VPN
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    set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
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    set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
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    andcc %g1, %g2, %g3             ! get Context
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    andcc %g1, %g2, %g3             ! get Context
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    bnz 0f                      ! Context is non-zero
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    bnz 0f                      ! Context is non-zero
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    PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
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    PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
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.endm
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.endm
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.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
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.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
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    /*
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    /*
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     * First, try to refill TLB from TSB.
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     */
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    ! TODO
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    /*
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     * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
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     * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
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     */
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     */
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.if (\tl > 0)
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.if (\tl > 0)
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    wrpr %g0, 1, %tl
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    wrpr %g0, 1, %tl
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.endif
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.endif
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate