Subversion Repositories HelenOS

Rev

Rev 1887 | Rev 1954 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 1887 Rev 1891
Line 42... Line 42...
42 
#include <arch/mm/tlb.h>
 42 
#include <arch/mm/tlb.h>
43 
#include <arch/mm/mmu.h>
 43 
#include <arch/mm/mmu.h>
44 
#include <arch/mm/tte.h>
 44 
#include <arch/mm/tte.h>
45 
#include <arch/trap/regwin.h>
 45 
#include <arch/trap/regwin.h>
46 
 
 46 
 
- 
 
 47 
#ifdef CONFIG_TSB
- 
 
 48 
#include <arch/mm/tsb.h>
- 
 
 49 
#endif
- 
 
 50 
 
47 
#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
 51 
#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
48 
#define TT_FAST_DATA_ACCESS_MMU_MISS        0x68
 52 
#define TT_FAST_DATA_ACCESS_MMU_MISS        0x68
49 
#define TT_FAST_DATA_ACCESS_PROTECTION      0x6c
 53 
#define TT_FAST_DATA_ACCESS_PROTECTION      0x6c
50 
 
 54 
 
51 
#define FAST_MMU_HANDLER_SIZE           128
 55 
#define FAST_MMU_HANDLER_SIZE           128
Line 54... Line 58...
54 
 
 58 
 
55 
.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
 59 
.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
56 
    /*
 60 
    /*
57 
     * First, try to refill TLB from TSB.
 61 
     * First, try to refill TLB from TSB.
58 
     */
 62 
     */
59 
    ! TODO
 - 
 
60 
 
 63 
 
- 
 
 64 
#ifdef CONFIG_TSB
- 
 
 65 
    ldxa [%g0] ASI_IMMU, %g1            ! read TSB Tag Target Register
- 
 
 66 
    ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2    ! read TSB 8K Pointer
- 
 
 67 
    ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4        ! 16-byte atomic load into %g4 and %g5
- 
 
 68 
    cmp %g1, %g4                    ! is this the entry we are looking for?
- 
 
 69 
    bne,pn %xcc, 0f
- 
 
 70 
    nop
- 
 
 71 
    stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG        ! copy mapping from ITSB to ITLB
- 
 
 72 
    retry
- 
 
 73 
#endif
- 
 
 74 
 
- 
 
 75 
0:
61 
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
 76 
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
62 
    PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
 77 
    PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
63 
.endm
 78 
.endm
64 
 
 79 
 
65 
.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
 80 
.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
66 
    /*
 81 
    /*
67 
     * First, try to refill TLB from TSB.
 82 
     * First, try to refill TLB from TSB.
68 
     */
 83 
     */
- 
 
 84 
 
- 
 
 85 
#ifdef CONFIG_TSB
- 
 
 86 
    ldxa [%g0] ASI_DMMU, %g1            ! read TSB Tag Target Register
- 
 
 87 
    srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this kernel miss?
- 
 
 88 
    brz,pn %g2, 0f
- 
 
 89 
    ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3    ! read TSB 8K Pointer
- 
 
 90 
    ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4        ! 16-byte atomic load into %g4 and %g5
- 
 
 91 
    cmp %g1, %g4                    ! is this the entry we are looking for?
- 
 
 92 
    bne,pn %xcc, 0f
- 
 
 93 
    nop
- 
 
 94 
    stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG        ! copy mapping from DTSB to DTLB
69 
    ! TODO
 95 
    retry
- 
 
 96 
#endif
70 
 
 97 
 
71 
    /*
 98 
    /*
72 
     * Second, test if it is the portion of the kernel address space
 99 
     * Second, test if it is the portion of the kernel address space
73 
     * which is faulting. If that is the case, immediately create
 100 
     * which is faulting. If that is the case, immediately create
74 
     * identity mapping for that page in DTLB. VPN 0 is excluded from
 101 
     * identity mapping for that page in DTLB. VPN 0 is excluded from
75 
     * this treatment.
 102 
     * this treatment.
76 
     *
 103 
     *
77 
     * Note that branch-delay slots are used in order to save space.
 104 
     * Note that branch-delay slots are used in order to save space.
78 
     */
 105 
     */
79 
 
 106 
0:
80 
    mov VA_DMMU_TAG_ACCESS, %g1
 107 
    mov VA_DMMU_TAG_ACCESS, %g1
81 
    ldxa [%g1] ASI_DMMU, %g1            ! read the faulting Context and VPN
 108 
    ldxa [%g1] ASI_DMMU, %g1            ! read the faulting Context and VPN
82 
    set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
 109 
    set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
83 
    andcc %g1, %g2, %g3             ! get Context
 110 
    andcc %g1, %g2, %g3             ! get Context
84 
    bnz 0f                      ! Context is non-zero
 111 
    bnz 0f                      ! Context is non-zero
Line 108... Line 135...
108 
    PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
 135 
    PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
109 
.endm
 136 
.endm
110 
 
 137 
 
111 
.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
 138 
.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
112 
    /*
 139 
    /*
113 
     * First, try to refill TLB from TSB.
 - 
 
114 
     */
 - 
 
115 
    ! TODO
 - 
 
116 
 
 - 
 
117 
    /*
 - 
 
118 
     * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
 140 
     * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
119 
     */
 141 
     */
- 
 
 142 
 
120 
.if (\tl > 0)
 143 
.if (\tl > 0)
121 
    wrpr %g0, 1, %tl
 144 
    wrpr %g0, 1, %tl
122 
.endif
 145 
.endif
123 
 
 146 
 
124 
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
 147 
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate