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| Rev 1865 | Rev 1870 | ||
|---|---|---|---|
| Line 60... | Line 60... | ||
| 60 | 60 | ||
| 61 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
61 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| 62 | PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss |
62 | PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss |
| 63 | .endm |
63 | .endm |
| 64 | 64 | ||
| 65 | .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER |
65 | .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl |
| 66 | /* |
66 | /* |
| 67 | * First, try to refill TLB from TSB. |
67 | * First, try to refill TLB from TSB. |
| 68 | */ |
68 | */ |
| 69 | ! TODO |
69 | ! TODO |
| 70 | 70 | ||
| Line 98... | Line 98... | ||
| 98 | * one of these two traps caused this trap, we just lower the trap |
98 | * one of these two traps caused this trap, we just lower the trap |
| 99 | * level and service the DTLB miss. In the end, we restart |
99 | * level and service the DTLB miss. In the end, we restart |
| 100 | * the offending SAVE or RESTORE. |
100 | * the offending SAVE or RESTORE. |
| 101 | */ |
101 | */ |
| 102 | 0: |
102 | 0: |
| - | 103 | .if (\tl > 0) |
|
| 103 | HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
104 | wrpr %g0, 1, %tl |
| - | 105 | .endif |
|
| 104 | 106 | ||
| 105 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
107 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| 106 | PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
108 | PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
| 107 | .endm |
109 | .endm |
| 108 | 110 | ||
| 109 | .macro FAST_DATA_ACCESS_PROTECTION_HANDLER |
111 | .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl |
| 110 | /* |
112 | /* |
| 111 | * First, try to refill TLB from TSB. |
113 | * First, try to refill TLB from TSB. |
| 112 | */ |
114 | */ |
| 113 | ! TODO |
115 | ! TODO |
| 114 | 116 | ||
| 115 | /* |
117 | /* |
| 116 | * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. |
118 | * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. |
| 117 | */ |
119 | */ |
| - | 120 | .if (\tl > 0) |
|
| 118 | HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
121 | wrpr %g0, 1, %tl |
| - | 122 | .endif |
|
| 119 | 123 | ||
| 120 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
124 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| 121 | PREEMPTIBLE_HANDLER fast_data_access_protection |
125 | PREEMPTIBLE_HANDLER fast_data_access_protection |
| 122 | .endm |
126 | .endm |
| 123 | 127 | ||
| 124 | .macro MEM_ADDRESS_NOT_ALIGNED_HANDLER |
- | |
| 125 | ba mem_address_not_aligned_handler |
- | |
| 126 | nop |
- | |
| 127 | .endm |
- | |
| 128 | - | ||
| 129 | /* |
- | |
| 130 | * Macro used to lower TL when a MMU trap is caused by |
- | |
| 131 | * the userspace register window spill or fill handler. |
- | |
| 132 | */ |
- | |
| 133 | .macro HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
- | |
| 134 | rdpr %tl, %g1 |
- | |
| 135 | sub %g1, 1, %g2 |
- | |
| 136 | brz %g2, 0f ! if TL was 1, skip |
- | |
| 137 | nop |
- | |
| 138 | wrpr %g2, 0, %tl ! TL-- |
- | |
| 139 | rdpr %tt, %g3 |
- | |
| 140 | cmp %g3, TT_SPILL_1_NORMAL |
- | |
| 141 | be 0f ! trap from spill_1_normal? |
- | |
| 142 | cmp %g3, TT_FILL_1_NORMAL |
- | |
| 143 | bne,a 0f ! trap from fill_1_normal? (negated condition) |
- | |
| 144 | wrpr %g1, 0, %tl ! TL++ |
- | |
| 145 | 0: |
- | |
| 146 | .endm |
- | |
| 147 | - | ||
| 148 | #endif /* __ASM__ */ |
128 | #endif /* __ASM__ */ |
| 149 | 129 | ||
| 150 | #endif |
130 | #endif |
| 151 | 131 | ||
| 152 | /** @} |
132 | /** @} |