WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/mm/tlb.h



 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(size_t entry)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;

/** Write IMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(size_t entry, uint64_t value)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;

 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(size_t entry)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;

/** Write DMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(size_t entry, uint64_t value)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;

 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(size_t entry)
{
    itlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;

 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(size_t entry)
{
    dtlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;

 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;

/** Write IMMU TLB Data Access Register.
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(int tlb, size_t entry,
    uint64_t value)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;

 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;

 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(int tlb, size_t entry,
    uint64_t value)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;

 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
{
    itlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_number = tlb;

 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
{
    dtlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_number = tlb;

Rev 3672	Rev 4490
Line 320...	Line 320...
320	* @param entry TLB Entry index.	320	* @param entry TLB Entry index.
321	*	321	*
322	* @return Current value of specified IMMU TLB Data Access	322	* @return Current value of specified IMMU TLB Data Access
323	* Register.	323	* Register.
324	*/	324	*/
325	static inline uint64_t itlb_data_access_read(index_t entry)	325	static inline uint64_t itlb_data_access_read(size_t entry)
326	{	326	{
327	itlb_data_access_addr_t reg;	327	itlb_data_access_addr_t reg;
328		328
329	reg.value = 0;	329	reg.value = 0;
330	reg.tlb_entry = entry;	330	reg.tlb_entry = entry;
Line 334...	Line 334...
334	/** Write IMMU TLB Data Access Register.	334	/** Write IMMU TLB Data Access Register.
335	*	335	*
336	* @param entry TLB Entry index.	336	* @param entry TLB Entry index.
337	* @param value Value to be written.	337	* @param value Value to be written.
338	*/	338	*/
339	static inline void itlb_data_access_write(index_t entry, uint64_t value)	339	static inline void itlb_data_access_write(size_t entry, uint64_t value)
340	{	340	{
341	itlb_data_access_addr_t reg;	341	itlb_data_access_addr_t reg;
342		342
343	reg.value = 0;	343	reg.value = 0;
344	reg.tlb_entry = entry;	344	reg.tlb_entry = entry;
Line 351...	Line 351...
351	* @param entry TLB Entry index.	351	* @param entry TLB Entry index.
352	*	352	*
353	* @return Current value of specified DMMU TLB Data Access	353	* @return Current value of specified DMMU TLB Data Access
354	* Register.	354	* Register.
355	*/	355	*/
356	static inline uint64_t dtlb_data_access_read(index_t entry)	356	static inline uint64_t dtlb_data_access_read(size_t entry)
357	{	357	{
358	dtlb_data_access_addr_t reg;	358	dtlb_data_access_addr_t reg;
359		359
360	reg.value = 0;	360	reg.value = 0;
361	reg.tlb_entry = entry;	361	reg.tlb_entry = entry;
Line 365...	Line 365...
365	/** Write DMMU TLB Data Access Register.	365	/** Write DMMU TLB Data Access Register.
366	*	366	*
367	* @param entry TLB Entry index.	367	* @param entry TLB Entry index.
368	* @param value Value to be written.	368	* @param value Value to be written.
369	*/	369	*/
370	static inline void dtlb_data_access_write(index_t entry, uint64_t value)	370	static inline void dtlb_data_access_write(size_t entry, uint64_t value)
371	{	371	{
372	dtlb_data_access_addr_t reg;	372	dtlb_data_access_addr_t reg;
373		373
374	reg.value = 0;	374	reg.value = 0;
375	reg.tlb_entry = entry;	375	reg.tlb_entry = entry;
Line 381...	Line 381...
381	*	381	*
382	* @param entry TLB Entry index.	382	* @param entry TLB Entry index.
383	*	383	*
384	* @return Current value of specified IMMU TLB Tag Read Register.	384	* @return Current value of specified IMMU TLB Tag Read Register.
385	*/	385	*/
386	static inline uint64_t itlb_tag_read_read(index_t entry)	386	static inline uint64_t itlb_tag_read_read(size_t entry)
387	{	387	{
388	itlb_tag_read_addr_t tag;	388	itlb_tag_read_addr_t tag;
389		389
390	tag.value = 0;	390	tag.value = 0;
391	tag.tlb_entry = entry;	391	tag.tlb_entry = entry;
Line 396...	Line 396...
396	*	396	*
397	* @param entry TLB Entry index.	397	* @param entry TLB Entry index.
398	*	398	*
399	* @return Current value of specified DMMU TLB Tag Read Register.	399	* @return Current value of specified DMMU TLB Tag Read Register.
400	*/	400	*/
401	static inline uint64_t dtlb_tag_read_read(index_t entry)	401	static inline uint64_t dtlb_tag_read_read(size_t entry)
402	{	402	{
403	dtlb_tag_read_addr_t tag;	403	dtlb_tag_read_addr_t tag;
404		404
405	tag.value = 0;	405	tag.value = 0;
406	tag.tlb_entry = entry;	406	tag.tlb_entry = entry;
Line 416...	Line 416...
416	* @param entry TLB Entry index.	416	* @param entry TLB Entry index.
417	*	417	*
418	* @return Current value of specified IMMU TLB Data Access	418	* @return Current value of specified IMMU TLB Data Access
419	* Register.	419	* Register.
420	*/	420	*/
421	static inline uint64_t itlb_data_access_read(int tlb, index_t entry)	421	static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
422	{	422	{
423	itlb_data_access_addr_t reg;	423	itlb_data_access_addr_t reg;
424		424
425	reg.value = 0;	425	reg.value = 0;
426	reg.tlb_number = tlb;	426	reg.tlb_number = tlb;
Line 431...	Line 431...
431	/** Write IMMU TLB Data Access Register.	431	/** Write IMMU TLB Data Access Register.
432	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	432	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
433	* @param entry TLB Entry index.	433	* @param entry TLB Entry index.
434	* @param value Value to be written.	434	* @param value Value to be written.
435	*/	435	*/
436	static inline void itlb_data_access_write(int tlb, index_t entry,	436	static inline void itlb_data_access_write(int tlb, size_t entry,
437	uint64_t value)	437	uint64_t value)
438	{	438	{
439	itlb_data_access_addr_t reg;	439	itlb_data_access_addr_t reg;
440		440
441	reg.value = 0;	441	reg.value = 0;
Line 451...	Line 451...
451	* @param entry TLB Entry index.	451	* @param entry TLB Entry index.
452	*	452	*
453	* @return Current value of specified DMMU TLB Data Access	453	* @return Current value of specified DMMU TLB Data Access
454	* Register.	454	* Register.
455	*/	455	*/
456	static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)	456	static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
457	{	457	{
458	dtlb_data_access_addr_t reg;	458	dtlb_data_access_addr_t reg;
459		459
460	reg.value = 0;	460	reg.value = 0;
461	reg.tlb_number = tlb;	461	reg.tlb_number = tlb;
Line 467...	Line 467...
467	*	467	*
468	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)	468	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
469	* @param entry TLB Entry index.	469	* @param entry TLB Entry index.
470	* @param value Value to be written.	470	* @param value Value to be written.
471	*/	471	*/
472	static inline void dtlb_data_access_write(int tlb, index_t entry,	472	static inline void dtlb_data_access_write(int tlb, size_t entry,
473	uint64_t value)	473	uint64_t value)
474	{	474	{
475	dtlb_data_access_addr_t reg;	475	dtlb_data_access_addr_t reg;
476		476
477	reg.value = 0;	477	reg.value = 0;
Line 486...	Line 486...
486	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	486	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
487	* @param entry TLB Entry index.	487	* @param entry TLB Entry index.
488	*	488	*
489	* @return Current value of specified IMMU TLB Tag Read Register.	489	* @return Current value of specified IMMU TLB Tag Read Register.
490	*/	490	*/
491	static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)	491	static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
492	{	492	{
493	itlb_tag_read_addr_t tag;	493	itlb_tag_read_addr_t tag;
494		494
495	tag.value = 0;	495	tag.value = 0;
496	tag.tlb_number = tlb;	496	tag.tlb_number = tlb;
Line 503...	Line 503...
503	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)	503	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
504	* @param entry TLB Entry index.	504	* @param entry TLB Entry index.
505	*	505	*
506	* @return Current value of specified DMMU TLB Tag Read Register.	506	* @return Current value of specified DMMU TLB Tag Read Register.
507	*/	507	*/
508	static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)	508	static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
509	{	509	{
510	dtlb_tag_read_addr_t tag;	510	dtlb_tag_read_addr_t tag;
511		511
512	tag.value = 0;	512	tag.value = 0;
513	tag.tlb_number = tlb;	513	tag.tlb_number = tlb;

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/include/mm/tlb.h – Rev 3672 → 4490