WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/mm/tlb.h



 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 

    tlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param entry TLB Entry index.

 * @param v Value to be written.
 */
static inline void dtlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
    membar();
}
 
/** Read DMMU TLB Tag Access Register.
 *
 * @return Current value of DMMU TLB Tag Access Register.

 * @param v Value to be written.
 */
static inline void dtlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
    membar();
}
 
/** Read ITLB Synchronous Fault Status Register.
 *
 * @return Current content of I-SFSR register.

 * @param v New value of D-SFSR register.
 */
static inline void dtlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
    membar();
}
 
/** Read DTLB Synchronous Fault Address Register.
 *
 * @return Current content of D-SFAR register.

    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
    membar();
}
 
extern void fast_instruction_access_mmu_miss(void);
extern void fast_data_access_mmu_miss(void);
extern void fast_data_access_protection(void);
 
extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
 
#endif
 
/** @}
 */
 

Rev 1787	Rev 1822
Line 24...	Line 24...
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
Line 225...	Line 225...
225	tlb_data_access_addr_t reg;	225	tlb_data_access_addr_t reg;
226		226
227	reg.value = 0;	227	reg.value = 0;
228	reg.tlb_entry = entry;	228	reg.tlb_entry = entry;
229	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);	229	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
230	flush();	230	membar();
231	}	231	}
232		232
233	/** Read IMMU TLB Tag Read Register.	233	/** Read IMMU TLB Tag Read Register.
234	*	234	*
235	* @param entry TLB Entry index.	235	* @param entry TLB Entry index.
Line 284...	Line 284...
284	* @param v Value to be written.	284	* @param v Value to be written.
285	*/	285	*/
286	static inline void dtlb_tag_access_write(uint64_t v)	286	static inline void dtlb_tag_access_write(uint64_t v)
287	{	287	{
288	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);	288	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
289	flush();	289	membar();
290	}	290	}
291		291
292	/** Read DMMU TLB Tag Access Register.	292	/** Read DMMU TLB Tag Access Register.
293	*	293	*
294	* @return Current value of DMMU TLB Tag Access Register.	294	* @return Current value of DMMU TLB Tag Access Register.
Line 314...	Line 314...
314	* @param v Value to be written.	314	* @param v Value to be written.
315	*/	315	*/
316	static inline void dtlb_data_in_write(uint64_t v)	316	static inline void dtlb_data_in_write(uint64_t v)
317	{	317	{
318	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);	318	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
319	flush();	319	membar();
320	}	320	}
321		321
322	/** Read ITLB Synchronous Fault Status Register.	322	/** Read ITLB Synchronous Fault Status Register.
323	*	323	*
324	* @return Current content of I-SFSR register.	324	* @return Current content of I-SFSR register.
Line 352...	Line 352...
352	* @param v New value of D-SFSR register.	352	* @param v New value of D-SFSR register.
353	*/	353	*/
354	static inline void dtlb_sfsr_write(uint64_t v)	354	static inline void dtlb_sfsr_write(uint64_t v)
355	{	355	{
356	asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);	356	asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
357	flush();	357	membar();
358	}	358	}
359		359
360	/** Read DTLB Synchronous Fault Address Register.	360	/** Read DTLB Synchronous Fault Address Register.
361	*	361	*
362	* @return Current content of D-SFAR register.	362	* @return Current content of D-SFAR register.
Line 405...	Line 405...
405	da.type = type;	405	da.type = type;
406	da.context = context_encoding;	406	da.context = context_encoding;
407	da.vpn = pg.vpn;	407	da.vpn = pg.vpn;
408		408
409	asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);	409	asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
410	flush();	410	membar();
411	}	411	}
412		412
413	extern void fast_instruction_access_mmu_miss(void);	413	extern void fast_instruction_access_mmu_miss(void);
414	extern void fast_data_access_mmu_miss(void);	414	extern void fast_data_access_mmu_miss(void);
415	extern void fast_data_access_protection(void);	415	extern void fast_data_access_protection(void);
416		416
417	extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);	417	extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
418		418
419	#endif	419	#endif
420		420
421	/** @}	421	/** @}
422	*/	422	*/
423		-

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/include/mm/tlb.h – Rev 1787 → 1822