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 */
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 */
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#ifndef KERN_sparc64_MMU_H_
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#ifndef KERN_sparc64_MMU_H_
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#define KERN_sparc64_MMU_H_
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#define KERN_sparc64_MMU_H_
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#if defined(US)
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/* LSU Control Register ASI. */
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/* LSU Control Register ASI. */
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#define ASI_LSU_CONTROL_REG     0x45    /**< Load/Store Unit Control Register. */
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#define ASI_LSU_CONTROL_REG     0x45    /**< Load/Store Unit Control Register. */
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#endif
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/* I-MMU ASIs. */
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/* I-MMU ASIs. */
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#define ASI_IMMU            0x50
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#define ASI_IMMU            0x50
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#define ASI_IMMU_TSB_8KB_PTR_REG    0x51   
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#define ASI_IMMU_TSB_8KB_PTR_REG    0x51   
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#define ASI_IMMU_TSB_64KB_PTR_REG   0x52
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#define ASI_IMMU_TSB_64KB_PTR_REG   0x52
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/* Virtual Addresses within ASI_IMMU. */
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/* Virtual Addresses within ASI_IMMU. */
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#define VA_IMMU_TSB_TAG_TARGET      0x0 /**< IMMU TSB tag target register. */
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#define VA_IMMU_TSB_TAG_TARGET      0x0 /**< IMMU TSB tag target register. */
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#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
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#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
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#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
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#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
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#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
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#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
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#if defined (US3)
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#define VA_IMMU_PRIMARY_EXTENSION   0x48    /**< IMMU TSB primary extension register */
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#define VA_IMMU_NUCLEUS_EXTENSION   0x58    /**< IMMU TSB nucleus extension register */
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#endif
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/* D-MMU ASIs. */
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/* D-MMU ASIs. */
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#define ASI_DMMU            0x58
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#define ASI_DMMU            0x58
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#define ASI_DMMU_TSB_8KB_PTR_REG    0x59   
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#define ASI_DMMU_TSB_8KB_PTR_REG    0x59   
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#define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
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#define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
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#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
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#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
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#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
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#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
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#define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
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#define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
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#define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
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#define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
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#define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
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#define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
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#if defined (US3)
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#define VA_DMMU_PRIMARY_EXTENSION   0x48    /**< DMMU TSB primary extension register */
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#define VA_DMMU_SECONDARY_EXTENSION 0x50    /**< DMMU TSB secondary extension register */
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#define VA_DMMU_NUCLEUS_EXTENSION   0x58    /**< DMMU TSB nucleus extension register */
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#endif
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#ifndef __ASM__
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#ifndef __ASM__
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <arch/barrier.h>
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#include <arch/barrier.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#if defined(US)
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/** LSU Control Register. */
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/** LSU Control Register. */
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typedef union {
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typedef union {
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    uint64_t value;
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    uint64_t value;
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    struct {
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    struct {
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        unsigned : 23;
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        unsigned : 23;
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        unsigned dc : 1;    /**< D-Cache enable. */
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        unsigned dc : 1;    /**< D-Cache enable. */
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        unsigned ic : 1;    /**< I-Cache enable. */
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        unsigned ic : 1;    /**< I-Cache enable. */
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    } __attribute__ ((packed));
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    } __attribute__ ((packed));
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} lsu_cr_reg_t;
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} lsu_cr_reg_t;
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#endif /* US */
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#endif /* !def __ASM__ */
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#endif /* !def __ASM__ */
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#endif
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#endif
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