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#define ASI_ITLB_DATA_ACCESS_REG    0x55
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#define ASI_ITLB_DATA_ACCESS_REG    0x55
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#define ASI_ITLB_TAG_READ_REG       0x56
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#define ASI_ITLB_TAG_READ_REG       0x56
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#define ASI_IMMU_DEMAP          0x57
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#define ASI_IMMU_DEMAP          0x57
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/* Virtual Addresses within ASI_IMMU. */
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/* Virtual Addresses within ASI_IMMU. */
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#define VA_IMMU_TAG_TARGET      0x0 /**< IMMU tag target register. */
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#define VA_IMMU_TSB_TAG_TARGET      0x0 /**< IMMU TSB tag target register. */
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#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
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#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
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#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
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#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
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#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
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#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
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/* D-MMU ASIs. */
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/* D-MMU ASIs. */
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#define ASI_DTLB_DATA_ACCESS_REG    0x5d
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#define ASI_DTLB_DATA_ACCESS_REG    0x5d
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#define ASI_DTLB_TAG_READ_REG       0x5e
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#define ASI_DTLB_TAG_READ_REG       0x5e
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#define ASI_DMMU_DEMAP          0x5f
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#define ASI_DMMU_DEMAP          0x5f
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/* Virtual Addresses within ASI_DMMU. */
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/* Virtual Addresses within ASI_DMMU. */
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#define VA_DMMU_TAG_TARGET      0x0 /**< DMMU tag target register. */
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#define VA_DMMU_TSB_TAG_TARGET      0x0 /**< DMMU TSB tag target register. */
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#define VA_PRIMARY_CONTEXT_REG      0x8 /**< DMMU primary context register. */
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#define VA_PRIMARY_CONTEXT_REG      0x8 /**< DMMU primary context register. */
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#define VA_SECONDARY_CONTEXT_REG    0x10    /**< DMMU secondary context register. */
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#define VA_SECONDARY_CONTEXT_REG    0x10    /**< DMMU secondary context register. */
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#define VA_DMMU_SFSR            0x18    /**< DMMU sync fault status register. */
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#define VA_DMMU_SFSR            0x18    /**< DMMU sync fault status register. */
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#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
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#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
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#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
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#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */