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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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 /** @addtogroup sparc64mm 
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/** @addtogroup sparc64mm  
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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#ifndef __sparc64_MMU_H__
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#ifndef __sparc64_MMU_H__
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#define __sparc64_MMU_H__
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#define __sparc64_MMU_H__
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#include <arch/asm.h>
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#include <arch/barrier.h>
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#include <arch/types.h>
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#include <typedefs.h>
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/** LSU Control Register ASI. */
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/** LSU Control Register ASI. */
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#define ASI_LSU_CONTROL_REG     0x45    /**< Load/Store Unit Control Register. */
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#define ASI_LSU_CONTROL_REG     0x45    /**< Load/Store Unit Control Register. */
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/** I-MMU ASIs. */
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/** I-MMU ASIs. */
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#define ASI_IMMU            0x50
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#define ASI_IMMU            0x50
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#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
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#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
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#define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
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#define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
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#define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
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#define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
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#define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
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#define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
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#ifndef __ASM__
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#include <arch/asm.h>
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#include <arch/barrier.h>
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#include <arch/types.h>
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#include <typedefs.h>
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/** LSU Control Register. */
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/** LSU Control Register. */
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union lsu_cr_reg {
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union lsu_cr_reg {
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    uint64_t value;
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    uint64_t value;
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    struct {
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    struct {
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    } __attribute__ ((packed));
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    } __attribute__ ((packed));
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};
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};
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typedef union lsu_cr_reg lsu_cr_reg_t;
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typedef union lsu_cr_reg lsu_cr_reg_t;
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#define immu_enable()   immu_set(true)
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#define immu_disable()  immu_set(false)
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#define dmmu_enable()   dmmu_set(true)
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#define dmmu_disable()  dmmu_set(false)
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/** Disable or Enable IMMU. */
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#endif /* !__ASM__ */
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static inline void immu_set(bool enable)
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{
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    lsu_cr_reg_t cr;
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    cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
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    cr.im = enable;
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    asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
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    membar();
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}
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/** Disable or Enable DMMU. */
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static inline void dmmu_set(bool enable)
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{
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    lsu_cr_reg_t cr;
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    cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
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    cr.dm = enable;
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    asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
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    membar();
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}
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#endif
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#endif
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 /** @}
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/** @}
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 */
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 */
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