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#define read_barrier()      \
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#define read_barrier()      \
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    asm volatile ("membar #LoadLoad\n" ::: "memory")
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    asm volatile ("membar #LoadLoad\n" ::: "memory")
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#define write_barrier()     \
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#define write_barrier()     \
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    asm volatile ("membar #StoreStore\n" ::: "memory")
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    asm volatile ("membar #StoreStore\n" ::: "memory")
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static inline void flush(uintptr_t addr)
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{
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    asm volatile ("flush %0\n" :: "r" (addr) : "memory");
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}
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/** Flush Instruction Memory instruction. */
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/** Flush Instruction Memory instruction. */
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static inline void flush(void)
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static inline void flush_blind(void)
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{
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{
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    /*
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    /*
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     * The FLUSH instruction takes address parameter.
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     * The FLUSH instruction takes address parameter.
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     * As such, it may trap if the address is not found in DTLB.
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     * As such, it may trap if the address is not found in DTLB.
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     *
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     *
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static inline void membar(void)
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static inline void membar(void)
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{
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{
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    asm volatile ("membar #Sync\n");
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    asm volatile ("membar #Sync\n");
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}
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}
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#define smc_coherence(a)    \
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{               \
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    write_barrier();    \
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    flush((a));     \
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}
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#endif
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#endif
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/** @}
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/** @}
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 */
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 */